mlsanityData to 14 Oct 2026

FPGA Divide-and-Conquer Placement using Deep Reinforcement Learning

arXiv 2404.13061 ↗First posted 11 Apr 2024cs.AR cs.AI cs.LGcited by 0

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Abstract (arXiv)

This paper introduces the problem of learning to place logic blocks in Field-Programmable Gate Arrays (FPGAs) and a learning-based method. In contrast to previous search-based placement algorithms, we instead employ Reinforcement Learning (RL) with the goal of minimizing wirelength. In addition to our preliminary learning results, we also evaluated a novel decomposition to address the nature of large search space when placing many blocks on a chipboard. Empirical experiments evaluate the effectiveness of the learning and decomposition paradigms on FPGA placement tasks.

Key facts. No citing papers in the map yet (data through 14 Oct 2026). Builds on 9 of its 19 references that are in the map. First posted on arXiv 11 Apr 2024.

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9 of 19 references.

References · 9

  1. 2015Deep Residual Learning for Image Recognitioncited by 52,096
  2. 2017Proximal Policy Optimization Algorithmscited by 15,215
  3. 2017Graph Attention Networkscited by 8,923
  4. 2020A Closer Look at Invalid Action Masking in Policy Gradient Algorithmscited by 171
  5. 2020Chip Placement with Deep Reinforcement Learningcited by 83
  6. 2021Exploration in Deep Reinforcement Learning: From Single-Agent to Multiagent Domaincited by 58
  7. 2021On Joint Learning for Solving Placement and Routing in Chip Designcited by 44
  8. 2022MaskPlace: Fast Chip Placement via Reinforced Visual Representation Learningcited by 43
  9. 2023ChiPFormer: Transferable Chip Placement via Offline Decision Transformercited by 42

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  1. 2026Component Centric Placement Using Deep Reinforcement Learning
  2. 2024Reinforcement Learning Policy as Macro Regulator Rather than Macro Placer
  3. 2024Chip Placement with Diffusion Models
  4. 2026How Can Reinforcement Learning Achieve Expert-level Placement?
  5. 2026RollPlace: Improving Macro Placement via Monte Carlo Rollout Search
  6. 2024Retrieval-Guided Reinforcement Learning for Boolean Circuit Minimization
  7. 2023INVICTUS: Optimizing Boolean Logic Circuit Synthesis via Synergistic Learning and Search
  8. 2024Chiplet Placement Order Exploration Based on Learning to Rank with Graph Representation