mlsanityData to 7 Oct 2026

FracBNN: Accurate and FPGA-Efficient Binary Neural Networks with Fractional Activations

arXiv 2012.12206 ↗First posted 22 Dec 2020cs.LG cs.CVcited by 30

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Abstract (arXiv)

Binary neural networks (BNNs) have 1-bit weights and activations. Such networks are well suited for FPGAs, as their dominant computations are bitwise arithmetic and the memory requirement is also significantly reduced. However, compared to start-of-the-art compact convolutional neural network (CNN) models, BNNs tend to produce a much lower accuracy on realistic datasets such as ImageNet. In addition, the input layer of BNNs has gradually become a major compute bottleneck, because it is conventionally excluded from binarization to avoid a large accuracy loss. This work proposes FracBNN, which exploits fractional activations to substantially improve the accuracy of BNNs. Specifically, our approach employs a dual-precision activation scheme to compute features with up to two bits, using an additional sparse binary convolution. We further binarize the input layer using a novel thermometer encoding. Overall, FracBNN preserves the key benefits of conventional BNNs, where all convolutional layers are computed in pure binary MAC operations (BMACs). We design an efficient FPGA-based accelerator for our novel BNN model that supports the fractional activations. To evaluate the performance of FracBNN under a resource-constrained scenario, we implement the entire optimized network architecture on an embedded FPGA (Xilinx Ultra96v2). Our experiments on ImageNet show that FracBNN achieves an accuracy comparable to MobileNetV2, surpassing the best-known BNN design on FPGAs with an increase of 28.9% in top-1 accuracy and a 2.5x reduction in model size. FracBNN also outperforms a recently introduced BNN model with an increase of 2.4% in top-1 accuracy while using the same model size. On the embedded FPGA device, FracBNN demonstrates the ability of real-time image classification.

Key facts. Cited by 30 papers in the map (data through 7 Oct 2026). First posted on arXiv 22 Dec 2020.

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Citing papers per year: 2021: 7; 2022: 3; 2023: 4; 2024: 9; 2025: 4; 2026: 3.

30 papers.

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  1. 2024FlightLLM: Efficient Large Language Model Inference with a Complete Mapping Flow on FPGAscited by 60
  2. 2021PokeBNN: A Binary Pursuit of Lightweight Accuracycited by 48
  3. 2021A comprehensive review of Binary Neural Networkcited by 44
  4. 2024Convolutional Differentiable Logic Gate Networkscited by 37
  5. 2023Understanding the Potential of FPGA-Based Spatial Acceleration for Large Language Model Inferencecited by 29
  6. 2021Pareto-Optimal Quantized ResNet Is Mostly 4-bitcited by 26
  7. 2021Quantization Backdoors to Deep Learning Commercial Frameworkscited by 25
  8. 2023BiBench: Benchmarking and Analyzing Network Binarizationcited by 22
  9. 2021Enabling Design Methodologies and Future Trends for Edge AI: Specialization and Co-designcited by 13
  10. 2022A Brain-Inspired Low-Dimensional Computing Classifier for Inference on Tiny Devicescited by 11
  11. 2023Low-Precision Mixed-Computation Models for Inference on Edgecited by 4
  12. 2025COBRA: Algorithm-Architecture Co-optimized Binary Transformer Accelerator for Edge Inferencecited by 4
18 more
  1. 2021RBNN: Memory-Efficient Reconfigurable Deep Binary Neural Network with IP Protection for Internet of Thingscited by 3
  2. 2023Input Layer Binarization with Bit-Plane Encodingcited by 3
  3. 2024PikeLPN: Mitigating Overlooked Inefficiencies of Low-Precision Neural Networkscited by 3
  4. 2021A Low-Cost Neural ODE with Depthwise Separable Convolution for Edge Domain Adaptation on FPGAscited by 2
  5. 2022RepBNN: towards a precise Binary Neural Network with Enhanced Feature Map via Repeatingcited by 2
  6. 2025Dynamic Tsetlin Machine Accelerators for On-Chip Training at the Edge using FPGAscited by 2
  7. 2024Trainable Fixed-Point Quantization for Deep Learning Acceleration on FPGAscited by 1
  8. 2024Scheduled Knowledge Acquisition on Lightweight Vector Symbolic Architectures for Brain-Computer Interfacescited by 1
  9. 2024ZOBNN: Zero-Overhead Dependable Design of Binary Neural Networks with Deliberately Quantized Parameterscited by 1
  10. 2025Runtime Tunable Tsetlin Machines for Edge Inference on eFPGAscited by 1
  11. 2026TTQ: Activation-Aware Test-Time Quantization to Accelerate LLM Inference On The Flycited by 1
  12. 2026FPGN: Redefining Ultra-Fast Programmable Gate-based Neural Acceleration with Differentiable LUTscited by 1
  13. 2022Exploiting Kernel Compression on BNNscited by 0
  14. 2024ReActXGB: A Hybrid Binary Convolutional Neural Network Architecture for Improved Performance and Computational Efficiencycited by 0
  15. 2024Mitigating scalability challenges in LUT-based neural networks via pruning optimisationscited by 0
  16. 2024Efficiera Residual Networks: Hardware-Friendly Fully Binary Weight with 2-bit Activation Model Achieves Practical ImageNet Accuracycited by 0
  17. 2025End-to-end fully-binarized network design: from Generic Learned Thermometer to Block Pruningcited by 0
  18. 2026Pruning Binarized Neural Networks: A Dedicated Framework and Globally Weighted Algorithmscited by 0