NeuroBlend: Towards Low-Power yet Accurate Neural Network-Based Inference Engine Blending Binary and Fixed-Point Convolutions
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Abstract (arXiv)
This paper introduces NeuroBlend, a novel neural network architecture featuring a unique building block known as the Blend module. This module incorporates binary and fixed-point convolutions in its main and skip paths, respectively. There is a judicious deployment of batch normalizations on both main and skip paths inside the Blend module and in between consecutive Blend modules. Additionally, we present a compiler and hardware architecture designed to map NeuroBlend models onto FPGA devices, aiming to minimize inference latency while maintaining high accuracy. Our NeuroBlend-20 (NeuroBlend-18) model, derived from ResNet-20 (ResNet-18) trained on CIFAR-10 (CIFAR-100), achieves 88.0% (73.73%) classification accuracy, outperforming state-of-the-art binary neural networks by 0.8% (1.33%), with an inference time of 0.38ms per image, 1.4x faster than previous FPGA implementation for BNNs. Similarly, our BlendMixer model for CIFAR-10 attains 90.6% accuracy(1.59% less than full precision MLPMixer), with a 3.5x reduction in model size compared to full precision MLPMixer. Furthermore, leveraging DSP blocks for 48-bit bitwise logic operations enables low-power FPGA implementation, yielding a 2.5x reduction in power consumption.
Key facts. Cited by 4 papers in the map (data through 14 Oct 2026). First posted on arXiv 7 Jul 2023.
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Citing papers per year: 2024: 2; 2025: 1; 2026: 1.
4 papers.
- 2024Dynamic Co-Optimization Compiler: Leveraging Multi-Agent Reinforcement Learning for Enhanced DNN Accelerator Performancecited by 4
- 2024CHOSEN: Compilation to Hardware Optimization Stack for Efficient Vision Transformer Inferencecited by 2
- 2026FPGN: Redefining Ultra-Fast Programmable Gate-based Neural Acceleration with Differentiable LUTscited by 1
- 2025PerHalluEval: Persian Hallucination Evaluation Benchmark for Large Language Modelscited by 0
- 2026FPGN: Redefining Ultra-Fast Programmable Gate-based Neural Acceleration with Differentiable LUTs9 Jul 2026
- 2025PerHalluEval: Persian Hallucination Evaluation Benchmark for Large Language Models25 Sep 2025
- 2024CHOSEN: Compilation to Hardware Optimization Stack for Efficient Vision Transformer Inference17 Jul 2024
- 2024Dynamic Co-Optimization Compiler: Leveraging Multi-Agent Reinforcement Learning for Enhanced DNN Accelerator Performance11 Jul 2024
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- 2025Energy-Efficient FPGA Framework for Non-Quantized Convolutional Neural Networks
- 2024Kratos: An FPGA Benchmark for Unrolled DNNs with Fine-Grained Sparsity and Mixed Precision
- 2023DietCNN: Multiplication-free Inference for Quantized CNNs
- 2023Optimizing data-flow in Binary Neural Networks
- 2023PLUM: Improving Inference Efficiency By Leveraging Repetition-Sparsity Trade-Off
- 2026DiffLUT-Net: Differentiable Training of FPGA LUT Networks with Learnable Connectivity