CIMulator: A Comprehensive Simulation Platform for Computing-In-Memory Circuit Macros with Low Bit-Width and Real Memory Materials
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Abstract (arXiv)
This paper presents a simulation platform, namely CIMulator, for quantifying the efficacy of various synaptic devices in neuromorphic accelerators for different neural network architectures. Nonvolatile memory devices, such as resistive random-access memory, ferroelectric field-effect transistor, and volatile static random-access memory devices, can be selected as synaptic devices. A multilayer perceptron and convolutional neural networks (CNNs), such as LeNet-5, VGG-16, and a custom CNN named C4W-1, are simulated to evaluate the effects of these synaptic devices on the training and inference outcomes. The dataset used in the simulations are MNIST, CIFAR-10, and a white blood cell dataset. By applying batch normalization and appropriate optimizers in the training phase, neuromorphic systems with very low-bit-width or binary weights could achieve high pattern recognition rates that approach software-based CNN accuracy. We also introduce spiking neural networks with RRAM-based synaptic devices for the recognition of MNIST handwritten digits.
Key facts. No citing papers in the map yet (data through 14 Oct 2026). Builds on 8 of its 66 references that are in the map. First posted on arXiv 26 Jun 2023.
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References · 8
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- 2015Batch Normalization: Accelerating Deep Network Training by Reducing Internal Covariate Shiftcited by 7,005
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- 2016Quantized Neural Networks: Training Neural Networks with Low Precision Weights and Activationscited by 426
- 2020DNN+NeuroSim V2.0: An End-to-End Benchmarking Framework for Compute-in-Memory Accelerators for On-chip Trainingcited by 33
- 2017Mitigating Asymmetric Nonlinear Weight Update Effects in Hardware Neural Network based on Analog Resistive Synapsecited by 4
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- 2025Bellman Memory Units: A neuromorphic framework for synaptic reinforcement learning with an evolving network topology
- 2025Bruno: Backpropagation Running Undersampled for Novel device Optimization
- 2025NeuroSim V1.5: Improved Software Backbone for Benchmarking Compute-in-Memory Accelerators with Device and Circuit-level Non-idealities
- 2023Gradient-descent hardware-aware training and deployment for mixed-signal Neuromorphic processors
- 2026A Hardware-Aware Open-Source Framework for Design Space Exploration of Mixed-Signal Spiking Neural Networks ↗
- 2025SpikeFit: Towards Optimal Deployment of Spiking Networks on Neuromorphic Hardware
- 2025Optimizing Binary and Ternary Neural Network Inference on RRAM Crossbars using CIM-Explorer
- 2025Enabling Efficient Processing of Spiking Neural Networks with On-Chip Learning on Commodity Neuromorphic Processors for Edge AI Systems