mlsanityData to 7 Oct 2026

P2M: A Processing-in-Pixel-in-Memory Paradigm for Resource-Constrained TinyML Applications

arXiv 2203.04737 ↗First posted 7 Mar 2022cs.LG cs.AR cs.CVcited by 16

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Abstract (arXiv)

The demand to process vast amounts of data generated from state-of-the-art high resolution cameras has motivated novel energy-efficient on-device AI solutions. Visual data in such cameras are usually captured in the form of analog voltages by a sensor pixel array, and then converted to the digital domain for subsequent AI processing using analog-to-digital converters (ADC). Recent research has tried to take advantage of massively parallel low-power analog/digital computing in the form of near- and in-sensor processing, in which the AI computation is performed partly in the periphery of the pixel array and partly in a separate on-board CPU/accelerator. Unfortunately, high-resolution input images still need to be streamed between the camera and the AI processing unit, frame by frame, causing energy, bandwidth, and security bottlenecks. To mitigate this problem, we propose a novel Processing-in-Pixel-in-memory (P2M) paradigm, that customizes the pixel array by adding support for analog multi-channel, multi-bit convolution, batch normalization, and ReLU (Rectified Linear Units). Our solution includes a holistic algorithm-circuit co-design approach and the resulting P2M paradigm can be used as a drop-in replacement for embedding memory-intensive first few layers of convolutional neural network (CNN) models within foundry-manufacturable CMOS image sensor platforms. Our experimental results indicate that P2M reduces data transfer bandwidth from sensors and analog to digital conversions by ~21x, and the energy-delay product (EDP) incurred in processing a MobileNetV2 model on a TinyML use case for visual wake words dataset (VWW) by up to ~11x compared to standard near-processing or in-sensor implementations, without any significant drop in test accuracy.

Key facts. Cited by 16 papers in the map (data through 7 Oct 2026). Builds on 23 of its 62 references that are in the map. First posted on arXiv 7 Mar 2022.

Builds on

23 of 62 references.

References · 23

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11 more
  1. 2018RxNN: A Framework for Evaluating Deep Neural Networks on Resistive Crossbarscited by 17
  2. 2020Pre-defined Sparsity for Low-Complexity Convolutional Neural Networkscited by 15
  3. 2020Fully Embedding Fast Convolutional Networks on Pixel Processor Arrayscited by 13
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  5. 2021Can Deep Neural Networks be Converted to Ultra Low-Latency Spiking Neural Networks?cited by 9
  6. 2021AnalogNets: ML-HW Co-Design of Noise-robust TinyML Models and Always-On Analog Compute-in-Memory Acceleratorcited by 7
  7. 2022PISA: A Binary-Weight Processing-In-Sensor Accelerator for Edge Image Processingcited by 4
  8. 2020IMAC: In-memory multi-bit Multiplication andACcumulation in 6T SRAM Arraycited by 3
  9. 2020Fundamental Limits on Energy-Delay-Accuracy of In-memory Architectures in Inference Applicationscited by 3
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  11. 2021A Reconfigurable Convolution-in-Pixel CMOS Image Sensor Architecturecited by 2

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Citing papers per year: 2022: 5; 2023: 3; 2024: 5; 2025: 1; 2026: 2.

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