UNIT: Unifying Tensorized Instruction Compilation
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Abstract (arXiv)
Because of the increasing demand for computation in DNN, researchers develope both hardware and software mechanisms to reduce the compute and memory burden. A widely adopted approach is to use mixed precision data types. However, it is hard to leverage mixed precision without hardware support because of the overhead of data casting. Hardware vendors offer tensorized instructions for mixed-precision tensor operations, like Intel VNNI, Tensor Core, and ARM-DOT. These instructions involve a computing idiom that reduces multiple low precision elements into one high precision element. The lack of compilation techniques for this makes it hard to utilize these instructions: Using vendor-provided libraries for computationally-intensive kernels is inflexible and prevents further optimizations, and manually writing hardware intrinsics is error-prone and difficult for programmers. Some prior works address this problem by creating compilers for each instruction. This requires excessive effort when it comes to many tensorized instructions. In this work, we develop a compiler framework to unify the compilation for these instructions -- a unified semantics abstraction eases the integration of new instructions, and reuses the analysis and transformations. Tensorized instructions from different platforms can be compiled via UNIT with moderate effort for favorable performance. Given a tensorized instruction and a tensor operation, UNIT automatically detects the applicability, transforms the loop organization of the operation,and rewrites the loop body to leverage the tensorized instruction. According to our evaluation, UNIT can target various mainstream hardware platforms. The generated end-to-end inference model achieves 1.3x speedup over Intel oneDNN on an x86 CPU, 1.75x speedup over Nvidia cuDNN on an NvidiaGPU, and 1.13x speedup over a carefully tuned TVM solution for ARM DOT on an ARM CPU.
Key facts. Cited by 10 papers in the map (data through 7 Oct 2026). Builds on 10 of its 48 references that are in the map. First posted on arXiv 21 Jan 2021.
Builds on
10 of 48 references.
References · 10
- 2017Mixed Precision Trainingcited by 1,135
- 2018Learning to Optimize Tensor Programscited by 138
- 2018Tensor Comprehensions: Framework-Agnostic High-Performance Machine Learning Abstractionscited by 84
- 2018Glow: Graph Lowering Compiler Techniques for Neural Networkscited by 73
- 2018TVM: An Automated End-to-End Optimizing Compiler for Deep Learningcited by 62
- 2018Optimizing CNN Model Inference on CPUscited by 29
- 2018Relay: A New IR for Machine Learning Frameworkscited by 24
- 2020Efficient Execution of Quantized Deep Learning Models: A Compiler Approachcited by 12
- 2020Automatic Kernel Generation for Volta Tensor Corescited by 8
- 2020PolyDL: Polyhedral Optimizations for Creation of High Performance DL primitivescited by 2
Built on by
Citing papers per year: 2021: 1; 2022: 3; 2023: 1; 2024: 1; 2025: 3; 2026: 1.
10 papers.
- 2022TensorIR: An Abstraction for Automatic Tensorized Program Optimizationcited by 38
- 2022Hidet: Task-Mapping Programming Paradigm for Deep Learning Tensor Programscited by 28
- 2023ArchGym: An Open-Source Gymnasium for Machine Learning Assisted Architecture Designcited by 6
- 2025PyGraph: Robust Compiler Support for CUDA Graphs in PyTorchcited by 3
- 2025REASONING COMPILER: LLM-Guided Optimizations for Efficient Model Servingcited by 3
- 2025Neptune: Advanced ML Operator Fusion for Locality and Parallelism on GPUscited by 3
- 2021Joint Program and Layout Transformations to enable Convolutional Operators on Specialized Hardware based on Constraint Programmingcited by 1
- 2024Automating Energy-Efficient GPU Kernel Generation: A Fast Search-Based Compilation Approachcited by 1
- 2022ALT: Boosting Deep Learning Performance by Breaking the Wall between Graph and Operator Level Optimizationscited by 0
- 2026HIERA: Workload-Aware Planning Across Implementation Spaces for GPU Kernel Optimizationcited by 0
- 2026HIERA: Workload-Aware Planning Across Implementation Spaces for GPU Kernel Optimization21 Aug 2026
- 2025Neptune: Advanced ML Operator Fusion for Locality and Parallelism on GPUs9 Oct 2025
- 2025REASONING COMPILER: LLM-Guided Optimizations for Efficient Model Serving2 Jun 2025
- 2025PyGraph: Robust Compiler Support for CUDA Graphs in PyTorch25 Mar 2025
- 2024Automating Energy-Efficient GPU Kernel Generation: A Fast Search-Based Compilation Approach28 Nov 2024
- 2023ArchGym: An Open-Source Gymnasium for Machine Learning Assisted Architecture Design15 Jun 2023
- 2022ALT: Boosting Deep Learning Performance by Breaking the Wall between Graph and Operator Level Optimizations22 Oct 2022
- 2022Hidet: Task-Mapping Programming Paradigm for Deep Learning Tensor Programs18 Oct 2022
- 2022TensorIR: An Abstraction for Automatic Tensorized Program Optimization9 Jul 2022
- 2021Joint Program and Layout Transformations to enable Convolutional Operators on Specialized Hardware based on Constraint Programming10 Apr 2021