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SCALE-Sim: Systolic CNN Accelerator Simulator

arXiv 1811.02883 ↗First posted 16 Oct 2018cs.DC cs.ARcited by 26

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Abstract (arXiv)

Systolic Arrays are one of the most popular compute substrates within Deep Learning accelerators today, as they provide extremely high efficiency for running dense matrix multiplications. However, the research community lacks tools to insights on both the design trade-offs and efficient mapping strategies for systolic-array based accelerators. We introduce Systolic CNN Accelerator Simulator (SCALE-Sim), which is a configurable systolic array based cycle accurate DNN accelerator simulator. SCALE-Sim exposes various micro-architectural features as well as system integration parameters to the designer to enable comprehensive design space exploration. This is the first systolic-array simulator tuned for running DNNs to the best of our knowledge. Using SCALE-Sim, we conduct a suite of case studies and demonstrate the effect of bandwidth, data flow and aspect ratio on the overall runtime and energy of Deep Learning kernels across vision, speech, text, and games. We believe that these insights will be highly beneficial to architects and ML practitioners.

Key facts. Cited by 26 papers in the map (data through 7 Oct 2026). First posted on arXiv 16 Oct 2018.

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Citing papers per year: 2021: 12; 2022: 9; 2023: 3; 2024: 1; 2025: 1.

26 papers.

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  1. 2021FLAT: An Optimized Dataflow for Mitigating Attention Bottleneckscited by 38
  2. 2021Auto-Split: A General Framework of Collaborative Edge-Cloud AIcited by 29
  3. 2021Energon: Towards Efficient Acceleration of Transformers Using Dynamic Sparse Attentioncited by 26
  4. 2021Mind Mappings: Enabling Efficient Algorithm-Accelerator Mapping Space Searchcited by 24
  5. 2021S2TA: Exploiting Structured Sparsity for Energy-Efficient Mobile CNN Accelerationcited by 19
  6. 2021Control Variate Approximation for DNN Acceleratorscited by 11
  7. 2024TransAxx: Efficient Transformers with Approximate Computingcited by 6
  8. 2021TENT: Efficient Quantization of Neural Networks on the tiny Edge with Tapered FixEd PoiNTcited by 4
  9. 2022Scale-out Systolic Arrayscited by 4
  10. 2022QAPPA: Quantization-Aware Power, Performance, and Area Modeling of DNN Acceleratorscited by 4
  11. 2023SGCN: Exploiting Compressed-Sparse Features in Deep Graph Convolutional Network Acceleratorscited by 4
  12. 2023Heterogeneous Integration of In-Memory Analog Computing Architectures with Tensor Processing Unitscited by 4
14 more
  1. 2022QADAM: Quantization-Aware DNN Accelerator Modeling for Pareto-Optimalitycited by 3
  2. 2022Integration of a systolic array based hardware accelerator into a DNN operator auto-tuning frameworkcited by 3
  3. 2021S2Engine: A Novel Systolic Architecture for Sparse Convolutional Neural Networkscited by 2
  4. 2022QUIDAM: A Framework for Quantization-Aware DNN Accelerator and Model Co-Explorationcited by 2
  5. 2022Design of High-Throughput Mixed-Precision CNN Accelerators on FPGAcited by 2
  6. 2021Self-Adaptive Reconfigurable Arrays (SARA): Using ML to Assist Scaling GEMM Accelerationcited by 1
  7. 2021CREW: Computation Reuse and Efficient Weight Storage for Hardware-accelerated MLPs and RNNscited by 1
  8. 2021Design and Scaffolded Training of an Efficient DNN Operator for Computer Vision on the Edgecited by 1
  9. 2022PhotoFourier: A Photonic Joint Transform Correlator-Based Neural Network Acceleratorcited by 1
  10. 2023Slice-and-Forge: Making Better Use of Caches for Graph Convolutional Network Acceleratorscited by 1
  11. 2025SpikeX: Exploring Accelerator Architecture and Network-Hardware Co-Optimization for Sparse Spiking Neural Networkscited by 1
  12. 2021A Construction Kit for Efficient Low Power Neural Network Accelerator Designscited by 0
  13. 2022Compiler-Driven Simulation of Reconfigurable Hardware Acceleratorscited by 0
  14. 2022DRAGON (Differentiable Graph Execution) : A suite of Hardware Simulation and Optimization tools for Modern AI/Non-AI Workloadscited by 0