RepTC: Representation-Aware Optimization for Efficient Traffic Classification on Edge IoT Devices
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Abstract (arXiv)
Traffic classification (TC) is crucial to secure Internet of Things (IoT) networks, whose edge nodes often operate under privacy, bandwidth, and energy constraints. Yet, encrypted payloads and limited computing power make accurate, real-time TC a challenging task. Existing learning-based TC approaches often fix the input configuration a priori, even though it directly influences both predictive performance and computational cost. This paper presents RepTC, a representation-aware hardware-constrained strategy that addresses session-level TC through joint model and input optimization. The method co-optimizes network architecture, session length, and header preprocessing; this enables joint control of model complexity, input scale, and data representation within a unified resource-constrained design space. The proposed approach enforces microcontroller-class constraints on memory, model size, and computation, and yields compact models deployable on low-power edge devices. A gateway monitors traffic by aggregating sessions and either performs inference locally or offloads to a low-power edge node. Both scenarios are validated on heterogeneous embedded hardware, including a Raspberry Pi 3B+, STM32 Nucleo-F401RE, and XIAO ESP32-C3, spanning Cortex-A, Cortex-M, and RISC-V processor architectures; measured inference latency ranges from 0.63 to 18.59 ms, with MCU-side inference energy between 0.50 and 1.41 mJ per session. RepTC yields configurations that achieve high accuracy on a variety of established benchmarks: 96.21% on ISCX VPN-nonVPN, 99.62% on USTC-TFC2016, and 99.97% on Edge-IIoTset; at the same time, model size and computational requirements were reduced by up to three orders of magnitude compared with state-of-the-art methods. The results show that representation-aware optimization can improve efficiency while preserving competitive classification performance.
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References · 14
- 2020Efficient Transformers: A Surveycited by 790
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- 2023Neural Architecture Search: Insights from 1000 Paperscited by 139
- 2018CMSIS-NN: Efficient Neural Network Kernels for Arm Cortex-M CPUscited by 121
- 2017Deep Packet: A Novel Approach For Encrypted Traffic Classification Using Deep Learningcited by 70
- 2020μNAS: Constrained Neural Architecture Search for Microcontrollerscited by 55
- 2023MicroNAS: Memory and Latency Constrained Hardware-Aware Neural Architecture Search for Time Series Classification on Microcontrollerscited by 8
- 2018Low-latency Networking: Where Latency Lurks and How to Tame Itcited by 7
- 2021FENXI: Deep-learning Traffic Analytics at the Edgecited by 5
- 2025Tiny Neural Networks for Session-Level Traffic Classificationcited by 5
- 2025Energy-Efficient Deep Learning for Traffic Classification on Microcontrollerscited by 4
- 2025Fast Data Aware Neural Architecture Search via Supernet Accelerated Evaluationcited by 3
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