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OmniRouting: A Semantic-Coupled Multimodal Benchmark for Constraint-Aware Spatial Reasoning in PCB Routing

arXiv 2608.04434 ↗First posted 5 Aug 2026cs.CVcited by 0

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Abstract (arXiv)

Recent large language models (LLMs) have demonstrated remarkable progress in constraint-aware navigation, maze reasoning, and graph reasoning. However, their ability to reason about complex routing problems under strict geometric, topological, and electrical constraints remains largely unexplored, despite routing being one of the most challenging and critical stages of electronic design automation (EDA). To bridge this gap, we introduce OmniRouting, the first large-scale benchmark designed to evaluate LLMs on printed-circuit-board (PCB) routing reasoning under real-world industrial design-rule, manufacturability, and connectivity constraints. OmniRouting contains 1,681 industrial-grade schematic-coupled PCB designs, including board geometries, routable component placements by human engineers, footprints, pad locations, netlists, stackup information, and routing constraints. The benchmark comprises four tasks: (1) geometric routing reasoning, generating physically valid copper traces, vias, and layer assignments to connect circuit nets within constrained board regions; (2) design-rule-aware routing reasoning, producing routable layouts that satisfy clearance, trace-width, via, obstacle-avoidance, and board-boundary constraints; (3) electrical functionality reasoning, preserving schematic-specified connectivity while reasoning over net names and functional roles to produce electrically correct routing; and (4) tool-augmented agentic routing, leveraging external tools for tasks (1)-(3). Our results reveal substantial limitations of current LMMs in PCB routing, including weak path-planning capabilities, poor adherence to design-rule constraints, and inconsistent preservation of electrical functionality. We will open-source all benchmark data, evaluation code, and tool interfaces to facilitate future research.

Key facts. No citing papers in the map yet (data through 7 Oct 2026). Builds on 10 of its 36 references that are in the map. First posted on arXiv 5 Aug 2026.

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10 of 36 references.

References · 10

  1. 2024SpatialVLM: Endowing Vision-Language Models with Spatial Reasoning Capabilitiescited by 679
  2. 2020Topological Planning with Transformers for Vision-and-Language Navigationcited by 115
  3. 2024GraphInstruct: Empowering Large Language Models with Graph Understanding and Reasoning Capabilitycited by 57
  4. 2023Can Large Language Models be Good Path Planners? A Benchmark and Investigation on Spatial-temporal Reasoningcited by 49
  5. 2024GraphArena: Evaluating and Exploring Large Language Models on Graph Computationcited by 48
  6. 2025AlphaMaze: Enhancing Large Language Models' Spatial Intelligence via GRPOcited by 33
  7. 2019A Deep Reinforcement Learning Approach for Global Routingcited by 20
  8. 2025MazeEval: A Benchmark for Testing Sequential Decision-Making in Language Modelscited by 8
  9. 2020Circuit Routing Using Monte Carlo Tree Search and Deep Neural Networkscited by 6
  10. 2026OmniSch: A Multimodal PCB Schematic Benchmark For Structured Diagram Visual Reasoningcited by 2

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  1. 2026OmniLayout: A Schematic-Coupled Multimodal Benchmark for Constraint-Aware Geometric Reasoning in PCB Layout
  2. 2025ChipMind: Retrieval-Augmented Reasoning for Long-Context Circuit Design Specifications
  3. 2026Circuit-MLLM: Topological Logic-Guided Latent-Space Visual Reasoning for Circuit Schematic Understanding
  4. 2026CircuitReason-1k: Benchmarking Long-Horizon Visual-to-Symbolic Reasoning inElectrical Circuits
  5. 2025A Large Language Model Powered Integrated Circuit Footprint Geometry Understanding
  6. 2026PCBWorld: A Benchmark Environment for Engine-Grounded PCB Design Automation
  7. 2026BenchCAD: A Comprehensive, Industry-Standard Benchmark for Programmatic CAD
  8. 2026PlaceReasoner-Beta: Reasoning-Driven Macro Placement and Benchmarking