Reconfigurable Computing Challenge: Real-Time Graph Neural Networks for Online Event Selection in Big Science
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Abstract (arXiv)
Graph neural networks are increasingly adopted in trigger systems for collider experiments, where strict latency and throughput constraints render deployment on embedded platforms challenging. As detectors move towards higher granularity, the number of inputs per inference increase and FPGA-only solutions face resource bottlenecks. This work presents an end-to-end demonstrator for the real-time deployment of a dynamic Graph Neural Network for the Belle II electromagnetic calorimeter hardware trigger on the AMD Versal VCK190, leveraging both FPGA fabric and AI Engine tiles. We develop a Python-based semi-automated design flow covering operator fusion, partitioning, mapping, spatial parallelization, and kernel-level optimization. Our design achieves a throughput of 2.94 million events per second at an end-to-end latency of 7.15 microseconds. Compared to the FPGA-only baseline, this represents a 53% throughput improvement while reducing DSP utilization from 99% to 19% at 29% AI Engine tile utilization. To validate the deployment, an interactive visualization pipeline enables real-time monitoring of inference results on the physical demonstrator.
Key facts. No citing papers in the map yet (data through 14 Oct 2026). Builds on 8 of its 19 references that are in the map. First posted on arXiv 11 May 2026.
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References · 8
- 2016FINN: A Framework for Fast, Scalable Binarized Neural Network Inferencecited by 150
- 2020Computing Graph Neural Networks: A Survey from Algorithms to Acceleratorscited by 81
- 2020Automatic heterogeneous quantization of deep neural networks for low-latency inference on the edge for particle detectorscited by 80
- 2021Applications and Techniques for Fast Machine Learning in Sciencecited by 32
- 2025hls4ml: A Flexible, Open-Source Platform for Deep Learning Acceleration on Reconfigurable Hardwarecited by 9
- 2025AIE4ML: An End-to-End Framework for Compiling Neural Networks for the Next Generation of AMD AI Enginescited by 5
- 2025From Loop Nests to Silicon: Mapping AI Workloads onto AMD NPUs with MLIR-AIRcited by 2
- 2025Real-Time Graph-based Point Cloud Networks on FPGAs via Stall-Free Deep Pipeliningcited by 1
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