Formal Mechanistic Interpretability: Automated Circuit Discovery with Provable Guarantees
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Abstract (arXiv)
*Automated circuit discovery* is a central tool in mechanistic interpretability for identifying the internal components of neural networks responsible for specific behaviors. While prior methods have made significant progress, they typically depend on heuristics or approximations and do not offer provable guarantees over continuous input domains for the resulting circuits. In this work, we leverage recent advances in neural network verification to propose a suite of automated algorithms that yield circuits with *provable guarantees*. We focus on three types of guarantees: (1) *input domain robustness*, ensuring the circuit agrees with the model across a continuous input region; (2) *robust patching*, certifying circuit alignment under continuous patching perturbations; and (3) *minimality*, formalizing and capturing a wide array of various notions of succinctness. Interestingly, we uncover a diverse set of novel theoretical connections among these three families of guarantees, with critical implications for the convergence of our algorithms. Finally, we conduct experiments with state-of-the-art verifiers on various vision models, showing that our algorithms yield circuits with substantially stronger robustness guarantees than standard circuit discovery methods, establishing a principled foundation for provable circuit discovery.
Key facts. Cited by 10 papers in the map (data through 7 Oct 2026). Builds on 93 of its 116 references that are in the map. First posted on arXiv 18 Feb 2026.
Builds on
93 of 116 references.
References · 93
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38 more
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50 most cited of 93 All 93 (JSON)
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Citing papers per year: 2026: 10.
10 papers.
- 2026Certified Circuits: Stability Guarantees for Mechanistic Circuitscited by 4
- 2026When Attribution Patching Lies: Diagnosis and a Second-Order Correctioncited by 2
- 2026Provably Explaining Neural Additive Modelscited by 1
- 2026Unifying Formal Explanations: A Complexity-Theoretic Perspectivecited by 1
- 2026From Circuit Evidence to Mechanistic Theory: An Inductive Logic Approachcited by 1
- 2026Verified SHAP: Provable Bounds for Exact Shapley Values of Neural Networkscited by 0
- 2026IFCLoRA: Topology-Aware Rank Allocation for Parameter-Efficient Fine-Tuningcited by 0
- 2026LAWFUL: Law-Aligned Witness for Faithful Use of Latentscited by 0
- 2026The Misery of Mechanistic Interpretability: A Formal Perspectivecited by 0
- 2026Representational Simplicity and Circuit Size Dissociate in a Threshold-Dependent Way: A Controlled Test via Adversarial Trainingcited by 0
- 2026Representational Simplicity and Circuit Size Dissociate in a Threshold-Dependent Way: A Controlled Test via Adversarial Training27 Sep 2026
- 2026The Misery of Mechanistic Interpretability: A Formal Perspective14 Sep 2026
- 2026LAWFUL: Law-Aligned Witness for Faithful Use of Latents26 Jul 2026
- 2026IFCLoRA: Topology-Aware Rank Allocation for Parameter-Efficient Fine-Tuning24 Jul 2026
- 2026When Attribution Patching Lies: Diagnosis and a Second-Order Correction5 Jun 2026
- 2026Verified SHAP: Provable Bounds for Exact Shapley Values of Neural Networks22 May 2026
- 2026From Circuit Evidence to Mechanistic Theory: An Inductive Logic Approach20 May 2026
- 2026Certified Circuits: Stability Guarantees for Mechanistic Circuits26 Feb 2026
- 2026Unifying Formal Explanations: A Complexity-Theoretic Perspective20 Feb 2026
- 2026Provably Explaining Neural Additive Models19 Feb 2026