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Hardware Software Optimizations for Fast Model Recovery on Reconfigurable Architectures

arXiv 2512.06113 ↗First posted 5 Dec 2025cs.AR cs.LGcited by 0

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Abstract (arXiv)

Model Recovery (MR) is a core primitive for physical AI and real-time digital twins, but GPUs often execute MR inefficiently due to iterative dependencies, kernel-launch overheads, underutilized memory bandwidth, and high data-movement latency. We present MERINDA, an FPGA-accelerated MR framework that restructures computation as a streaming dataflow pipeline. MERINDA exploits on-chip locality through BRAM tiling, fixed-point kernels, and the concurrent use of LUT fabric and carry-chain adders to expose fine-grained spatial parallelism while minimizing off-chip traffic. This hardware-aware formulation removes synchronization bottlenecks and sustains high throughput across the iterative updates in MR. On representative MR workloads, MERINDA delivers up to 6.3x fewer cycles than an FPGA-based LTC baseline, enabling real-time performance for time-critical physical systems.

Key facts. No citing papers in the map yet (data through 7 Oct 2026). Builds on 18 of its 49 references that are in the map. First posted on arXiv 5 Dec 2025.

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References · 18

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6 more
  1. 2024Recovering implicit physics model under real-world constraintscited by 4
  2. 2020Accelerating ODE-Based Neural Networks on Low-Cost FPGAscited by 3
  3. 2019EdgeDRNN: Enabling Low-latency Recurrent Neural Network Edge Inferencecited by 2
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  6. 2023OpenPARF: An Open-Source Placement and Routing Framework for Large-Scale Heterogeneous FPGAs with Deep Learning Toolkitcited by 1

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