mlsanityData to 7 Oct 2026

Mozart: A Chiplet Ecosystem-Accelerator Codesign Framework for Composable Bespoke Application Specific Integrated Circuits

arXiv 2510.08873 ↗First posted 10 Oct 2025cs.ARcited by 0

On the map: Efficient LLM inference and serving → Serving systems and request scheduling

Abstract (arXiv)

Modern AI acceleration faces a fundamental challenge: conventional assumptions about memory requirements, batching effectiveness, and latency-throughput tradeoffs are systemwide generalizations that ignore the heterogeneous computational patterns of individual neural network operators. However, going towards network-level customization and operator-level heterogeneity incur substantial Non-Recurring Engineering (NRE) costs. While chiplet-based approaches have been proposed to amortize NRE costs, reuse opportunities remain limited without carefully identifying which chiplets are truly necessary. This paper introduces Mozart, a chiplet ecosystem and accelerator codesign framework that systematically constructs low cost bespoke application-specific integrated circuits (BASICs). BASICs leverage operator-level disaggregation to explore chiplet and memory heterogeneity, tensor fusion, and tensor parallelism, with place-and-route validation ensuring physical implementability. The framework also enables constraint-aware system-level optimization across deployment contexts ranging from datacenter inference serving to edge computing in autonomous vehicles. The evaluation confirms that with just 8 strategically selected chiplets, Mozart-generated composite BASICs achieve 43.5%, 25.4%, 67.7%, and 78.8% reductions in energy, energy-cost product, energy-delay product (EDP), and energy-delay-cost product compared to traditional homogeneous accelerators. For datacenter LLM serving, Mozart achieves 15-19% energy reduction and 35-39% energy-cost improvement. In speculative decoding, Mozart delivers throughput improvements of 24.6-58.6% while reducing energy consumption by 38.6-45.6%. For autonomous vehicle perception, Mozart reduces energy-cost by 25.54% and energy by 10.53% under real-time constraints.

Key facts. No citing papers in the map yet (data through 7 Oct 2026). Placed in Serving systems and request scheduling, one of 12 directions in Efficient LLM inference and serving. Builds on 23 of its 69 references that are in the map. First posted on arXiv 10 Oct 2025.

Builds on

23 of 69 references.

Closest ancestors · 1

Same direction, newest first

  1. 2024DistServe: Disaggregating Prefill and Decoding for Goodput-optimized Large Language Model Serving18 Jan

Other references · 22

  1. 2020An Image is Worth 16x16 Words: Transformers for Image Recognition at Scalecited by 29,915
  2. 2022Generative Adversarial Networkscited by 5,603
  3. 2015You Only Look Once: Unified, Real-Time Object Detectioncited by 4,829
  4. 2022Fast Inference from Transformers via Speculative Decodingcited by 1,615
  5. 2019EfficientDet: Scalable and Efficient Object Detectioncited by 1,018
  6. 2023FlexGen: High-Throughput Generative Inference of Large Language Models with a Single GPUcited by 567
  7. 2023Splitwise: Efficient generative LLM inference using phase splittingcited by 536
  8. 2020MobileDets: Searching for Object Detection Architectures for Mobile Acceleratorscited by 55
  9. 2021CoSA: Scheduling by Constrained Optimization for Spatial Acceleratorscited by 22
  10. 2023A Survey on Deep Learning Hardware Accelerators for Heterogeneous HPC Platformscited by 21
  11. 2024Cambricon-LLM: A Chiplet-Based Hybrid Architecture for On-Device Inference of 70B LLMcited by 17
  12. 2019HyPar: Towards Hybrid Parallelism for Deep Learning Accelerator Arraycited by 15
10 more
  1. 2022DeFiNES: Enabling Fast Exploration of the Depth-first Scheduling Space for DNN Accelerators through Analytical Modelingcited by 12
  2. 2023Gemini: Mapping and Architecture Co-exploration for Large-scale DNN Chiplet Acceleratorscited by 7
  3. 2024SCAR: Scheduling Multi-Model AI Workloads on Heterogeneous Multi-Chiplet Module Acceleratorscited by 6
  4. 2014A Survey of Methods For Analyzing and Improving GPU Energy Efficiencycited by 5
  5. 2022Chiplet Actuary: A Quantitative Cost Model and Multi-Chiplet Architecture Explorationcited by 4
  6. 2025DOSA: Differentiable Model-Based One-Loop Search for DNN Acceleratorscited by 4
  7. 2025SoMa: Identifying, Exploring, and Understanding the DRAM Communication Scheduling Space for DNN Acceleratorscited by 3
  8. 2024Cocco: Hardware-Mapping Co-Exploration towards Memory Capacity-Communication Optimizationcited by 2
  9. 2024DFModel: Design Space Optimization of Large-Scale Systems Exploiting Dataflow Mappingscited by 2
  10. 2023Monad: Towards Cost-effective Specialization for Chiplet-based Spatial Acceleratorscited by 1

Built on by

Not cited yet.

Similar, not cited

Close in wording, no citation either way

  1. 2026Fengshui: Demystifying Chiplet Ecosystem and Bespoke Neural Network Accelerator Codesign ↗
  2. 2026Mozart: Modularized and Efficient MoE Training on 3.5D Wafer-Scale Chiplet Architectures
  3. 2026Energy Efficient Software Hardware CoDesign for Machine Learning: From TinyML to Large Language Models
  4. 2026Beacon: LLM Multi-Agent Driven Hardware Design Space Exploration for Heterogeneous Multi-Chiplet Deep Learning Accelerators ↗
  5. 2026Agentic Design Space Exploration for Joint Hardware Configuration Selection and Mapping of AI Inference Workloads on Heterogeneous Edge SoCs
  6. 2026HYDRA: A Heterogeneous Chiplet DSE Framework for Serving Dynamic Hybrid LLM Workloads
  7. 2026Agent Factories for High Level Synthesis: How Far Can General-Purpose Coding Agents Go in Hardware Optimization?
  8. 2025Hardware-Algorithm Co-Optimization of Early-Exit Neural Networks for Multi-Core Edge Accelerators