SPAD: Specialized Prefill and Decode Hardware for Disaggregated LLM Inference
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Abstract (arXiv)
Large Language Models (LLMs) have gained popularity in recent years, driving up the demand for inference. LLM inference is composed of two phases with distinct characteristics: a compute-bound prefill phase followed by a memory-bound decode phase. To efficiently serve LLMs, prior work proposes prefill-decode disaggregation to run each phase on separate hardware. However, existing hardware poorly matches the different requirements of each phase. Current datacenter GPUs and TPUs follow a more-is-better design philosophy that maximizes compute and memory resources, causing memory bandwidth underutilization in the prefill phase and compute underutilization in the decode phase. Such underutilization directly translates into increased serving costs. This paper proposes SPAD (Specialized Prefill and Decode hardware), adopting a less-is-more methodology to design specialized chips tailored to the distinct characteristics of prefill and decode phases. The proposed Prefill Chips have larger systolic arrays and use cost-effective GDDR memory, whereas the proposed Decode Chips retain high memory bandwidth but reduce compute capacity. Compared to modeled H100s, simulations show that the proposed Prefill Chips deliver 8% higher prefill performance on average at 52% lower hardware cost, while the proposed Decode Chips achieve 97% of the decode performance with 28% lower TDP. End-to-end simulations on production traces show that SPAD reduces hardware cost by 19%-41% and TDP by 2%-17% compared to modeled baseline clusters while offering the same performance. Even when models and workloads change, SPAD can reallocate either type of chip to run either phase and still achieve 11%-43% lower hardware costs, demonstrating the longevity of the SPAD design.
Key facts. Cited by 6 papers in the map (data through 14 Oct 2026). Builds on 25 of its 64 references that are in the map. First posted on arXiv 9 Oct 2025.
Builds on
25 of 64 references.
References · 25
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13 more
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Built on by
Citing papers per year: 2025: 1; 2026: 5.
6 papers.
- 2025Efficient MoE Serving in the Memory-Bound Regime: Balance Activated Experts, Not Tokenscited by 5
- 2026Prefilling-dLLM: Predictive Prefilling for Long-Context Inference in Diffusion Language Modelscited by 3
- 2026Towards Green AI: Decoding the Energy of LLM Inference in Software Developmentcited by 2
- 2026Salca: A Sparsity-Aware Hardware Accelerator for Efficient Long-Context Attention Decodingcited by 0
- 2026From Tensor Buffer to Distributed Memory Hierarchy: A Survey of KV Cache Management for LLM Servingcited by 0
- 2026NELSSA: A GPU-PNM Heterogeneous System for Mixed-Length LLM Serving via Length-based Request Placementcited by 0
- 2026NELSSA: A GPU-PNM Heterogeneous System for Mixed-Length LLM Serving via Length-based Request Placement29 Jul 2026
- 2026From Tensor Buffer to Distributed Memory Hierarchy: A Survey of KV Cache Management for LLM Serving30 Jun 2026
- 2026Prefilling-dLLM: Predictive Prefilling for Long-Context Inference in Diffusion Language Models9 Jun 2026
- 2026Salca: A Sparsity-Aware Hardware Accelerator for Efficient Long-Context Attention Decoding27 Apr 2026
- 2026Towards Green AI: Decoding the Energy of LLM Inference in Software Development5 Feb 2026
- 2025Efficient MoE Serving in the Memory-Bound Regime: Balance Activated Experts, Not Tokens10 Dec 2025
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