mlsanityData to 14 Oct 2026

Weight Mapping Properties of a Dual Tree Single Clock Adiabatic Capacitive Neuron

arXiv 2509.18143 ↗First posted 15 Sep 2025cs.ET cs.AI cs.LGcited by 0

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Abstract (arXiv)

Dual Tree Single Clock (DTSC) Adiabatic Capacitive Neuron (ACN) circuits offer the potential for highly energy-efficient Artificial Neural Network (ANN) computation in full custom analog IC designs. The efficient mapping of Artificial Neuron (AN) abstract weights, extracted from the software-trained ANNs, onto physical ACN capacitance values has, however, yet to be fully researched. In this paper, we explore the unexpected hidden complexities, challenges and properties of the mapping, as well as, the ramifications for IC designers in terms accuracy, design and implementation. We propose an optimal, AN to ACN methodology, that promotes smaller chip sizes and improved overall classification accuracy, necessary for successful practical deployment. Using TensorFlow and Larq software frameworks, we train three different ANN networks and map their weights into the energy-efficient DTSC ACN capacitance value domain to demonstrate 100% functional equivalency. Finally, we delve into the impact of weight quantization on ACN performance using novel metrics related to practical IC considerations, such as IC floor space and comparator decision-making efficacy.

Key facts. No citing papers in the map yet (data through 14 Oct 2026). Builds on 6 of its 39 references that are in the map. First posted on arXiv 15 Sep 2025.

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6 of 39 references.

References · 6

  1. 2013Estimating or Propagating Gradients Through Stochastic Neurons for Conditional Computationcited by 2,079
  2. 2016Quantized Neural Networks: Training Neural Networks with Low Precision Weights and Activationscited by 426
  3. 2020Binary Neural Networks: A Surveycited by 190
  4. 2021A comprehensive review of Binary Neural Networkcited by 45
  5. 2022An Adiabatic Capacitive Artificial Neuron with RRAM-based Threshold Detection for Energy-Efficient Neuromorphic Computingcited by 1
  6. 2025Adiabatic Capacitive Neuron: An Energy-Efficient Functional Unit for Artificial Neural Networkscited by 1

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  2. 2025NeuroSim V1.5: Improved Software Backbone for Benchmarking Compute-in-Memory Accelerators with Device and Circuit-level Non-idealities
  3. 2023Quantization of Deep Neural Networks to facilitate self-correction of weights on Phase Change Memory-based analog hardware
  4. 2025A 33.6-136.2 TOPS/W Nonlinear Analog Computing-In-Memory Macro for Multi-bit LSTM Accelerator in 65 nm CMOS ↗
  5. 2021A Configurable BNN ASIC using a Network of Programmable Threshold Logic Standard Cells
  6. 2026You Only Charge Once 2.0 : A End-to-End Analog Computing-in-Memory Architecture with Reconfigurable Switched Capacitors
  7. 2024A 1.6-fJ/Spike Subthreshold Analog Spiking Neuron in 28 nm CMOS ↗
  8. 2021PR-CIM: a Variation-Aware Binary-Neural-Network Framework for Process-Resilient Computation-in-memory