How to keep pushing ML accelerator performance? Know your rooflines!
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Abstract (arXiv)
The rapidly growing importance of Machine Learning (ML) applications, coupled with their ever-increasing model size and inference energy footprint, has created a strong need for specialized ML hardware architectures. Numerous ML accelerators have been explored and implemented, primarily to increase task-level throughput per unit area and reduce task-level energy consumption. This paper surveys key trends toward these objectives for more efficient ML accelerators and provides a unifying framework to understand how compute and memory technologies/architectures interact to enhance system-level efficiency and performance. To achieve this, the paper introduces an enhanced version of the roofline model and applies it to ML accelerators as an effective tool for understanding where various execution regimes fall within roofline bounds and how to maximize performance and efficiency under the rooline. Key concepts are illustrated with examples from state-of-the-art designs, with a view towards open research opportunities to further advance accelerator performance.
Key facts. Cited by 6 papers in the map (data through 14 Oct 2026). First posted on arXiv 22 May 2025.
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Citing papers per year: 2025: 2; 2026: 4.
6 papers.
- 2025POLARON: Precision-aware On-device Learning and Adaptive Runtime-cONfigurable AI accelerationcited by 4
- 2025Hardware-Aware YOLO Compression for Low-Power Edge AI on STM32U5 for Weeds Detection in Digital Agriculturecited by 1
- 2026CORVET: A CORDIC-Powered, Resource-Frugal Mixed-Precision Vector Processing Engine for High-Throughput AIoT applicationscited by 1
- 2026Physical Foundation Models: Fixed hardware implementations of large-scale neural networkscited by 1
- 2026Neuromorphic Diffusion Language Models: Addressing Compute and Memory Bottlenecks via Sparsity and Block Denoisingcited by 0
- 2026Energy-Efficient Visual Inspection with FFT-Based CNNs and Adaptive Floating-Point Quantizationcited by 0
- 2026Energy-Efficient Visual Inspection with FFT-Based CNNs and Adaptive Floating-Point Quantization20 Aug 2026
- 2026Neuromorphic Diffusion Language Models: Addressing Compute and Memory Bottlenecks via Sparsity and Block Denoising24 Jul 2026
- 2026Physical Foundation Models: Fixed hardware implementations of large-scale neural networks30 Apr 2026
- 2026CORVET: A CORDIC-Powered, Resource-Frugal Mixed-Precision Vector Processing Engine for High-Throughput AIoT applications22 Feb 2026
- 2025Hardware-Aware YOLO Compression for Low-Power Edge AI on STM32U5 for Weeds Detection in Digital Agriculture11 Nov 2025
- 2025POLARON: Precision-aware On-device Learning and Adaptive Runtime-cONfigurable AI acceleration10 Jun 2025