T-REX: A 68-567 μs/token, 0.41-3.95 μJ/token Transformer Accelerator with Reduced External Memory Access and Enhanced Hardware Utilization in 16nm FinFET
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Abstract (arXiv)
This work introduces novel training and post-training compression schemes to reduce external memory access during transformer model inference. Additionally, a new control flow mechanism, called dynamic batching, and a novel buffer architecture, termed a two-direction accessible register file, further reduce external memory access while improving hardware utilization.
Key facts. No citing papers in the map yet (data through 7 Oct 2026). Builds on 4 of its 21 references that are in the map. First posted on arXiv 1 Mar 2025.
Builds on
4 of 21 references.
References · 4
- 2020fairseq S2T: Fast Speech-to-Text Modeling with fairseqcited by 174
- 2022HeatViT: Hardware-Efficient Adaptive Token Pruning for Vision Transformerscited by 46
- 2022ViTCoD: Vision Transformer Acceleration via Dedicated Algorithm and Accelerator Co-Designcited by 41
- 2022ViTALiTy: Unifying Low-rank and Sparse Approximation for Vision Transformer Acceleration with a Linear Taylor Attentioncited by 29
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