mlsanityData to 14 Oct 2026

tuGEMM: Area-Power-Efficient Temporal Unary GEMM Architecture for Low-Precision Edge AI

arXiv 2412.17966 ↗First posted 23 Dec 2024cs.AR cs.AI cs.LGcited by 2

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Abstract (arXiv)

General matrix multiplication (GEMM) is a ubiquitous computing kernel/algorithm for data processing in diverse applications, including artificial intelligence (AI) and deep learning (DL). Recent shift towards edge computing has inspired GEMM architectures based on unary computing, which are predominantly stochastic and rate-coded systems. This paper proposes a novel GEMM architecture based on temporal-coding, called tuGEMM, that performs exact computation. We introduce two variants of tuGEMM, serial and parallel, with distinct area/power-latency trade-offs. Post-synthesis Power-Performance-Area (PPA) in 45 nm CMOS are reported for 2-bit, 4-bit, and 8-bit computations. The designs illustrate significant advantages in area-power efficiency over state-of-the-art stochastic unary systems especially at low precisions, e.g. incurring just 0.03 mm^2 and 9 mW for 4 bits, and 0.01 mm^2 and 4 mW for 2 bits. This makes tuGEMM ideal for power constrained mobile and edge devices performing always-on real-time sensory processing.

Key facts. Cited by 2 papers in the map (data through 14 Oct 2026). Builds on 9 of its 20 references that are in the map. First posted on arXiv 23 Dec 2024.

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9 of 20 references.

References · 9

  1. 2017In-Datacenter Performance Analysis of a Tensor Processing Unitcited by 618
  2. 2020The Computational Limits of Deep Learningcited by 193
  3. 2019Edge AI: On-Demand Accelerating Deep Neural Network Inference via Edge Computingcited by 152
  4. 2016Convolutional Neural Networks using Logarithmic Data Representationcited by 99
  5. 2018AI Benchmark: Running Deep Neural Networks on Android Smartphonescited by 75
  6. 2020Systolic Tensor Array: An Efficient Structured-Sparse GEMM Accelerator for Mobile CNN Inferencecited by 17
  7. 2017Mixed Low-precision Deep Learning Inference using Dynamic Fixed Pointcited by 4
  8. 2021A Microarchitecture Implementation Framework for Online Learning with Temporal Neural Networkscited by 4
  9. 2018Correlation Manipulating Circuits for Stochastic Computingcited by 3

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Cited by year (2026 to 14 Oct)

Citing papers per year: 2024: 1; 2025: 0; 2026: 1.

2 papers.

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  1. 2024tubGEMM: Energy-Efficient and Sparsity-Effective Temporal-Unary-Binary Based Matrix Multiply Unit
  2. 2025MVDRAM: Enabling GeMV Execution in Unmodified DRAM for Low-Bit LLM Acceleration
  3. 2025MEADOW: Memory-efficient Dataflow and Data Packing for Low Power Edge LLMs
  4. 2025PIM-LLM: A High-Throughput Hybrid PIM Architecture for 1-bit LLMs
  5. 2026TOM: A Ternary Read-only Memory Accelerator for LLM-powered Edge Intelligence
  6. 2021Edge AI without Compromise: Efficient, Versatile and Accurate Neurocomputing in Resistive Random-Access Memory
  7. 2025The Cambrian Explosion of Mixed-Precision Matrix Multiplication for Quantized Deep Learning Inference
  8. 2025TeLLMe: An Energy-Efficient Ternary LLM Accelerator for Prefilling and Decoding on Edge FPGAs