USEFUSE: Uniform Stride for Enhanced Performance in Fused Layer Architecture of Deep Neural Networks
Not on the map. Why?
Abstract (arXiv)
Convolutional Neural Networks (CNNs) are crucial in various applications, but their deployment on resource-constrained edge devices poses challenges. This study presents the Sum-of-Products (SOP) units for convolution, which utilize low-latency left-to-right bit-serial arithmetic to minimize response time and enhance overall performance. The study proposes a methodology for fusing multiple convolution layers to reduce off-chip memory communication and increase overall performance. An effective mechanism detects and skips inefficient convolutions after ReLU layers, minimizing power consumption without compromising accuracy. Furthermore, efficient tile movement guarantees uniform access to the fusion pyramid. An analysis demonstrates the utile stride strategy improves operational intensity. Two designs cater to varied demands: one focuses on minimal response time for mission-critical applications, and another focuses on resource-constrained devices with comparable latency. This approach notably reduced redundant computations, improving the efficiency of CNN deployment on edge devices.
Key facts. Cited by 1 paper in the map (data through 14 Oct 2026). Builds on 20 of its 65 references that are in the map. First posted on arXiv 18 Dec 2024.
Builds on
20 of 65 references.
References · 20
- 2019PyTorch: An Imperative Style, High-Performance Deep Learning Librarycited by 20,305
- 2014Very Deep Convolutional Networks for Large-Scale Image Recognitioncited by 15,364
- 2014Fully Convolutional Networks for Semantic Segmentationcited by 4,859
- 2020Plug-and-Play Image Restoration with Deep Denoiser Priorcited by 470
- 2017Bit Fusion: Bit-Level Dynamically Composable Architecture for Accelerating Deep Neural Networkscited by 109
- 2022Practical Blind Image Denoising via Swin-Conv-UNet and Data Synthesiscited by 86
- 2023A Study on ReLU and Softmax in Transformercited by 53
- 2018Automatically designing CNN architectures using genetic algorithm for image classificationcited by 48
- 2023Replacing softmax with ReLU in Vision Transformerscited by 44
- 2023ArtAdapter: Text-to-Image Style Transfer using Multi-Level Style Encoder and Explicit Adaptationcited by 40
- 2016Bit-pragmatic Deep Neural Network Computingcited by 32
- 2022AdaPT: Fast Emulation of Approximate DNN Accelerators in PyTorchcited by 11
8 more
- 2017Efficient B-mode Ultrasound Image Reconstruction from Sub-sampled RF Data using Deep Learningcited by 8
- 2017Fixed-point optimization of deep neural networks with adaptive step size retrainingcited by 6
- 2021ShortcutFusion: From Tensorflow to FPGA-based accelerator with reuse-aware memory allocation for shortcut datacited by 6
- 2022Design of High-Throughput Mixed-Precision CNN Accelerators on FPGAcited by 3
- 2023Low-Latency Online Multiplier with Reduced Activities and Minimized Interconnect for Inner Product Arrayscited by 3
- 2019CompRRAE: RRAM-based Convolutional Neural Network Accelerator with Reduced Computations through a Runtime Activation Estimationcited by 2
- 2020AFP-SRC: Identification of Antifreeze Proteins Using Sparse Representation Classifiercited by 2
- 2020CITISEN: A Deep Learning-Based Speech Signal-Processing Mobile Applicationcited by 1
Built on by
Citing papers per year: 2026: 1.
1 paper.