MCU-MixQ: A HW/SW Co-optimized Mixed-precision Neural Network Design Framework for MCUs
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Abstract (arXiv)
Mixed-precision neural network (MPNN) that utilizes just enough data width for the neural network processing is an effective approach to meet the stringent resources constraints including memory and computing of MCUs. Nevertheless, there is still a lack of sub-byte and mixed-precision SIMD operations in MCU-class ISA and the limited computing capability of MCUs remains underutilized, which further aggravates the computing bound encountered in neural network processing. As a result, the benefits of MPNNs cannot be fully unleashed. In this work, we propose to pack multiple low-bitwidth arithmetic operations within a single instruction multiple data (SIMD) instructions in typical MCUs, and then develop an efficient convolution operator by exploring both the data parallelism and computing parallelism in convolution along with the proposed SIMD packing. Finally, we further leverage Neural Architecture Search (NAS) to build a HW/SW co-designed MPNN design framework, namely MCU-MixQ. This framework can optimize both the MPNN quantization and MPNN implementation efficiency, striking an optimized balance between neural network performance and accuracy. According to our experiment results, MCU-MixQ achieves 2.1× and 1.4× speedup over CMix-NN and MCUNet respectively under the same resource constraints.
Key facts. Cited by 2 papers in the map (data through 7 Oct 2026). Builds on 21 of its 40 references that are in the map. First posted on arXiv 17 Jul 2024.
Builds on
21 of 40 references.
References · 21
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9 more
- 2022F8Net: Fixed-Point 8-bit Only Multiplication for Network Quantizationcited by 26
- 2023A Practical Mixed Precision Algorithm for Post-Training Quantizationcited by 23
- 2023Unified Data-Free Compression: Pruning and Quantization without Fine-Tuningcited by 22
- 2021Quantization and Deployment of Deep Neural Networks on Microcontrollerscited by 20
- 2020A Learning Framework for n-bit Quantized Neural Networks toward FPGAscited by 11
- 2022Pex: Memory-efficient Microcontroller Deep Learning through Partial Executioncited by 3
- 2021HiKonv: High Throughput Quantized Convolution With Novel Bit-wise Management and Computationcited by 2
- 2022DSP-Packing: Squeezing Low-precision Arithmetic into FPGA DSP Blockscited by 2
- 2024Differentiable Search for Finding Optimal Quantization Strategycited by 2
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Citing papers per year: 2025: 1; 2026: 1.
2 papers.