A Fully-Configurable Open-Source Software-Defined Digital Quantized Spiking Neural Core Architecture
Not on the map. Why?
Abstract (arXiv)
We introduce QUANTISENC, a fully configurable open-source software-defined digital quantized spiking neural core architecture to advance research in neuromorphic computing. QUANTISENC is designed hierarchically using a bottom-up methodology with multiple neurons in each layer and multiple layers in each core. The number of layers and neurons per layer can be configured via software in a top-down methodology to generate the hardware for a target spiking neural network (SNN) model. QUANTISENC uses leaky integrate and fire neurons (LIF) and current-based excitatory and inhibitory synapses (CUBA). The nonlinear dynamics of a neuron can be configured at run-time via programming its internal control registers. Each neuron performs signed fixed-point arithmetic with user-defined quantization and decimal precision. QUANTISENC supports all-to-all, one-to-one, and Gaussian connections between layers. Its hardware-software interface is integrated with a PyTorch-based SNN simulator. This integration allows to define and train an SNN model in PyTorch and evaluate the hardware performance (e.g., area, power, latency, and throughput) through FPGA prototyping and ASIC design. The hardware-software interface also takes advantage of the layer-based architecture and distributed memory organization of QUANTISENC to enable pipelining by overlapping computations on streaming data. Overall, the proposed software-defined hardware design methodology offers flexibility similar to that of high-level synthesis (HLS), but provides better hardware performance with zero hardware development effort. We evaluate QUANTISENC using three spiking datasets and show its superior performance against state-of the-art designs.
Key facts. Cited by 8 papers in the map (data through 7 Oct 2026). First posted on arXiv 2 Apr 2024.
Builds on
No reference list yet.
Built on by
Citing papers per year: 2025: 2; 2026: 6.
8 papers.
- 2025Improving Performance of Spike-based Deep Q-Learning using Ternary Neuronscited by 3
- 2026Hardware-accelerated graph neural networks: an alternative approach for neuromorphic event-based audio classification and keyword spotting on SoC FPGAcited by 2
- 2025Hardware-Accelerated Event-Graph Neural Networks for Low-Latency Time-Series Classification on SoC FPGAcited by 1
- 2026Spiking Neural Network inference on FPGAs with hls4mlcited by 1
- 2026Efficient Aspect Term Extraction using Spiking Neural Networkcited by 0
- 2026End-to-End Keyword Spotting on FPGA Using Graph Neural Networks with a Neuromorphic Auditory Sensorcited by 0
- 2026Scalable neuromorphic computing from autonomous spiking dynamics in a clockless reconfigurable chipcited by 0
- 2026Syn2Logic: End-to-End Neuromorphic Design Automationcited by 0
- 2026Syn2Logic: End-to-End Neuromorphic Design Automation26 Aug 2026
- 2026Spiking Neural Network inference on FPGAs with hls4ml8 Jun 2026
- 2026Scalable neuromorphic computing from autonomous spiking dynamics in a clockless reconfigurable chip15 May 2026
- 2026End-to-End Keyword Spotting on FPGA Using Graph Neural Networks with a Neuromorphic Auditory Sensor10 May 2026
- 2026Hardware-accelerated graph neural networks: an alternative approach for neuromorphic event-based audio classification and keyword spotting on SoC FPGA18 Feb 2026
- 2026Efficient Aspect Term Extraction using Spiking Neural Network10 Jan 2026
- 2025Improving Performance of Spike-based Deep Q-Learning using Ternary Neurons3 Jun 2025
- 2025Hardware-Accelerated Event-Graph Neural Networks for Low-Latency Time-Series Classification on SoC FPGA9 Mar 2025