Silicon Photonic 2.5D Interposer Networks for Overcoming Communication Bottlenecks in Scale-out Machine Learning Hardware Accelerators
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Abstract (arXiv)
Modern machine learning (ML) applications are becoming increasingly complex and monolithic (single chip) accelerator architectures cannot keep up with their energy efficiency and throughput demands. Even though modern digital electronic accelerators are gradually adopting 2.5D architectures with multiple smaller chiplets to improve scalability, they face fundamental limitations due to a reliance on slow metallic interconnects. This paper outlines how optical communication and computation can be leveraged in 2.5D platforms to realize energy-efficient and high throughput 2.5D ML accelerator architectures.
Key facts. Cited by 1 paper in the map (data through 14 Oct 2026). Builds on 8 of its 21 references that are in the map. First posted on arXiv 7 Mar 2024.
Builds on
8 of 21 references.
References · 8
- 2021CrossLight: A Cross-Layer Optimized Silicon Photonic Neural Network Acceleratorcited by 29
- 2021A Survey on Silicon Photonics for Deep Learningcited by 23
- 2022RecLight: A Recurrent Neural Network Accelerator with Integrated Silicon Photonicscited by 12
- 2023TRON: Transformer Neural Network Acceleration with Non-Coherent Silicon Photonicscited by 12
- 2023GHOST: A Graph Neural Network Accelerator using Silicon Photonicscited by 7
- 2023Machine Learning Accelerators in 2.5D Chiplet Platforms with Silicon Photonicscited by 5
- 2022ReSiPI: A Reconfigurable Silicon-Photonic 2.5D Chiplet Network with PCMs for Energy-Efficient Interposer Communicationcited by 3
- 2021DeFT: A Deadlock-Free and Fault-Tolerant Routing Algorithm for 2.5D Chiplet Networkscited by 2
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Citing papers per year: 2024: 1.
1 paper.