Machine Learning Accelerators in 2.5D Chiplet Platforms with Silicon Photonics
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Abstract (arXiv)
Domain-specific machine learning (ML) accelerators such as Google's TPU and Apple's Neural Engine now dominate CPUs and GPUs for energy-efficient ML processing. However, the evolution of electronic accelerators is facing fundamental limits due to the limited computation density of monolithic processing chips and the reliance on slow metallic interconnects. In this paper, we present a vision of how optical computation and communication can be integrated into 2.5D chiplet platforms to drive an entirely new class of sustainable and scalable ML hardware accelerators. We describe how cross-layer design and fabrication of optical devices, circuits, and architectures, and hardware/software codesign can help design efficient photonics-based 2.5D chiplet platforms to accelerate emerging ML workloads.
Key facts. Cited by 5 papers in the map (data through 7 Oct 2026). Builds on 11 of its 47 references that are in the map. First posted on arXiv 28 Jan 2023.
Builds on
11 of 47 references.
References · 11
- 2015U-Net: Convolutional Networks for Biomedical Image Segmentationcited by 19,604
- 2021CrossLight: A Cross-Layer Optimized Silicon Photonic Neural Network Acceleratorcited by 29
- 2021A Survey on Silicon Photonics for Deep Learningcited by 23
- 2019Digital Electronics and Analog Photonics for Convolutional Neural Networks (DEAP-CNNs)cited by 22
- 2021ROBIN: A Robust Optical Binary Neural Network Acceleratorcited by 15
- 2021An Electro-Photonic System for Accelerating Deep Neural Networkscited by 15
- 2020INDRA: Intrusion Detection using Recurrent Autoencoders in Automotive Embedded Systemscited by 12
- 2022RecLight: A Recurrent Neural Network Accelerator with Integrated Silicon Photonicscited by 12
- 2022A Silicon Photonic Accelerator for Convolutional Neural Networks with Heterogeneous Quantizationcited by 9
- 2022ReSiPI: A Reconfigurable Silicon-Photonic 2.5D Chiplet Network with PCMs for Energy-Efficient Interposer Communicationcited by 3
- 2021DeFT: A Deadlock-Free and Fault-Tolerant Routing Algorithm for 2.5D Chiplet Networkscited by 2
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Citing papers per year: 2023: 1; 2024: 3; 2025: 0; 2026: 1.
5 papers.
- 2024Accelerating Neural Networks for Large Language Models and Graph Processing with Silicon Photonicscited by 1
- 2024Silicon Photonic 2.5D Interposer Networks for Overcoming Communication Bottlenecks in Scale-out Machine Learning Hardware Acceleratorscited by 1
- 2023Towards Efficient Hyperdimensional Computing Using Photonicscited by 0
- 2024Optical Computing for Deep Neural Network Acceleration: Foundations, Recent Developments, and Emerging Directionscited by 0
- 2026Hardware Trojan Threats to Multi-Chiplet Photonic Neural Network Acceleratorscited by 0
- 2026Hardware Trojan Threats to Multi-Chiplet Photonic Neural Network Accelerators6 Sep 2026
- 2024Optical Computing for Deep Neural Network Acceleration: Foundations, Recent Developments, and Emerging Directions30 Jul 2024
- 2024Silicon Photonic 2.5D Interposer Networks for Overcoming Communication Bottlenecks in Scale-out Machine Learning Hardware Accelerators7 Mar 2024
- 2024Accelerating Neural Networks for Large Language Models and Graph Processing with Silicon Photonics12 Jan 2024
- 2023Towards Efficient Hyperdimensional Computing Using Photonics29 Nov 2023