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DenRAM: Neuromorphic Dendritic Architecture with RRAM for Efficient Temporal Processing with Delays

arXiv 2312.08960 ↗First posted 14 Dec 2023cs.ET eess.SPcited by 16

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Abstract (arXiv)

An increasing number of neuroscience studies are highlighting the importance of spatial dendritic branching in pyramidal neurons in the brain for supporting non-linear computation through localized synaptic integration. In particular, dendritic branches play a key role in temporal signal processing and feature detection, using coincidence detection (CD) mechanisms, made possible by the presence of synaptic delays that align temporally disparate inputs for effective integration. Computational studies on spiking neural networks further highlight the significance of delays for CD operations, enabling spatio-temporal pattern recognition within feed-forward neural networks without the need for recurrent architectures. In this work, we present DenRAM, the first realization of a spiking neural network with analog dendritic circuits, integrated into a 130nm technology node coupled with resistive memory (RRAM) technology. DenRAM's dendritic circuits use the RRAM devices to implement both delays and synaptic weights in the network. By configuring the RRAM devices to reproduce bio-realistic timescales, and through exploiting their heterogeneity, we experimentally demonstrate DenRAM's capability to replicate synaptic delay profiles, and efficiently implement CD for spatio-temporal pattern recognition. To validate the architecture, we conduct comprehensive system-level simulations on two representative temporal benchmarks, highlighting DenRAM's resilience to analog hardware noise, and its superior accuracy compared to recurrent architectures with an equivalent number of parameters. DenRAM not only brings rich temporal processing capabilities to neuromorphic architectures, but also reduces the memory footprint of edge devices, provides high accuracy on temporal benchmarks, and represents a significant step-forward in low-power real-time signal processing technologies.

Key facts. Cited by 16 papers in the map (data through 7 Oct 2026). First posted on arXiv 14 Dec 2023.

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Cited by year (2026 to 7 Oct)

Citing papers per year: 2024: 6; 2025: 7; 2026: 3.

16 papers.

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  1. 2024DelGrad: Exact event-based gradients for training delays and weights on spiking neuromorphic hardwarecited by 9
  2. 2024The Role of Temporal Hierarchy in Spiking Neural Networkscited by 4
  3. 2024Distributed Representations Enable Robust Multi-Timescale Symbolic Computation in Neuromorphic Hardwarecited by 3
  4. 2025Beyond Rate Coding: Surrogate Gradients Enable Spike Timing Learning in Spiking Neural Networkscited by 3
  5. 2026Hardware-accelerated graph neural networks: an alternative approach for neuromorphic event-based audio classification and keyword spotting on SoC FPGAcited by 2
  6. 2025Fundamental Survey on Neuromorphic Based Audio Classificationcited by 1
  7. 2025Hardware-Accelerated Event-Graph Neural Networks for Low-Latency Time-Series Classification on SoC FPGAcited by 1
  8. 2024Topology Optimization of Random Memristors for Input-Aware Dynamic SNNcited by 0
  9. 2024A frugal Spiking Neural Network for unsupervised classification of continuous multivariate temporal datacited by 0
  10. 2024TEXEL: A neuromorphic processor with on-chip learning for beyond-CMOS device integrationcited by 0
  11. 2025Dendritic Computing with Multi-Gate Ferroelectric Field-Effect Transistorscited by 0
  12. 2025mGRADE: Minimal Recurrent Gating Meets Delay Convolutions for Lightweight Sequence Modelingcited by 0
4 more
  1. 2025A High-Throughput Spiking Neural Network Processor Enabling Synaptic Delay Emulationcited by 0
  2. 2025Delays in Spiking Neural Networks: A State Space Model Approachcited by 0
  3. 2026DendroNN: Dendrocentric Neural Networks for Energy-Efficient Classification of Event-Based Datacited by 0
  4. 2026Scalable neuromorphic computing from autonomous spiking dynamics in a clockless reconfigurable chipcited by 0