mlsanityData to 14 Oct 2026

Sparq: A Custom RISC-V Vector Processor for Efficient Sub-Byte Quantized Inference

arXiv 2306.09905 ↗First posted 16 Jun 2023cs.ARcited by 1

Not on the map. Why?

Abstract (arXiv)

Convolutional Neural Networks (CNNs) are used in a wide range of applications, with full-precision CNNs achieving high accuracy at the expense of portability. Recent progress in quantization techniques has demonstrated that sub-byte Quantized Neural Networks (QNNs) achieve comparable or superior accuracy while significantly reducing the computational cost and memory footprint. However, sub-byte computation on commodity hardware is sub-optimal due to the lack of support for such precision. In this paper, we introduce Sparq, a Sub-byte vector Processor designed for the AcceleRation of QNN inference. This processor is based on a modified version of Ara, an open-source 64-bit RISC-V ``V'' compliant processor. Sparq is implemented in GLOBAL FOUNDRIES 22FDX FD-SOI technology and extends the Instruction Set Architecture (ISA) by adding a new multiply-shift-accumulate instruction to improve sub-byte computation effciency. The floating-point unit is also removed to minimize area and power usage. To demonstrate Sparq performance, we implement an ultra-low-precision (1-bit to 4-bit) vectorized conv2d operation taking advantage of the dedicated hardware. We show that Sparq can significantly accelerate sub-byte computations with respectively 3.2 times, and 1.7 times acceleration over an optimized 16-bit 2D convolution for 2-bit and 4-bit quantization.

Key facts. Cited by 1 paper in the map (data through 14 Oct 2026). Builds on 13 of its 21 references that are in the map. First posted on arXiv 16 Jun 2023.

Builds on

13 of 21 references.

References · 13

  1. 2019EfficientNet: Rethinking Model Scaling for Convolutional Neural Networkscited by 6,442
  2. 2016Aggregated Residual Transformations for Deep Neural Networkscited by 2,546
  3. 2016XNOR-Net: ImageNet Classification Using Binary Convolutional Neural Networkscited by 849
  4. 2019Learned Step Size Quantizationcited by 628
  5. 2015BinaryConnect: Training Deep Neural Networks with binary weights during propagationscited by 592
  6. 2021A White Paper on Neural Network Quantizationcited by 472
  7. 2019Differentiable Soft Quantization: Bridging Full-Precision and Low-Bit Neural Networkscited by 238
  8. 2018Bi-Real Net: Enhancing the Performance of 1-bit CNNs With Improved Representational Capability and Advanced Training Algorithmcited by 235
  9. 2018The ARM Scalable Vector Extensioncited by 9
  10. 2019Ara: A 1 GHz+ Scalable and Energy-Efficient RISC-V Vector Processor with Multi-Precision Floating Point Support in 22 nm FD-SOIcited by 5
  11. 2022A "New Ara" for Vector Computing: An Open Source Highly Efficient RISC-V V 1.0 Vector Processor Designcited by 5
  12. 2022LG-LSQ: Learned Gradient Linear Symmetric Quantizationcited by 3
1 more
  1. 2023Quark: An Integer RISC-V Vector Processor for Sub-Byte Quantized DNN Inferencecited by 2

Built on by

Cited by year

Citing papers per year: 2024: 1.

1 paper.

  1. 2024SPEED: A Scalable RISC-V Vector Processor Enabling Efficient Multi-Precision DNN Inferencecited by 2

Similar, not cited

Close in wording, no citation either way

  1. 2022FullPack: Full Vector Utilization for Sub-Byte Quantized Inference on General Purpose CPUs
  2. 2025MaRVIn: A Cross-Layer Mixed-Precision RISC-V Framework for DNN Inference, from ISA Extension to Hardware Acceleration
  3. 2026SPARQLe: Sub-Precision Activation Representation for Quantized LLM Inference
  4. 2021VS-Quant: Per-vector Scaled Quantization for Accurate Low-Precision Neural Network Inference
  5. 2021Post-Training Sparsity-Aware Quantization
  6. 2025Dual Precision Quantization for Efficient and Accurate Deep Neural Networks Inference
  7. 2023A Precision-Scalable RISC-V DNN Processor with On-Device Learning Capability at the Extreme Edge
  8. 2025MSQ: Memory-Efficient Bit Sparsification Quantization