HighLight: Efficient and Flexible DNN Acceleration with Hierarchical Structured Sparsity
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Abstract (arXiv)
Due to complex interactions among various deep neural network (DNN) optimization techniques, modern DNNs can have weights and activations that are dense or sparse with diverse sparsity degrees. To offer a good trade-off between accuracy and hardware performance, an ideal DNN accelerator should have high flexibility to efficiently translate DNN sparsity into reductions in energy and/or latency without incurring significant complexity overhead. This paper introduces hierarchical structured sparsity (HSS), with the key insight that we can systematically represent diverse sparsity degrees by having them hierarchically composed from multiple simple sparsity patterns. As a result, HSS simplifies the underlying hardware since it only needs to support simple sparsity patterns; this significantly reduces the sparsity acceleration overhead, which improves efficiency. Motivated by such opportunities, we propose a simultaneously efficient and flexible accelerator, named HighLight, to accelerate DNNs that have diverse sparsity degrees (including dense). Due to the flexibility of HSS, different HSS patterns can be introduced to DNNs to meet different applications' accuracy requirements. Compared to existing works, HighLight achieves a geomean of up to 6.4x better energy-delay product (EDP) across workloads with diverse sparsity degrees, and always sits on the EDP-accuracy Pareto frontier for representative DNNs
Key facts. Cited by 12 papers in the map (data through 13 Oct 2026). Builds on 24 of its 57 references that are in the map. First posted on arXiv 22 May 2023.
Builds on
24 of 57 references.
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12 more
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Citing papers per year: 2024: 7; 2025: 3; 2026: 2.
12 papers.
- 2024BitMoD: Bit-serial Mixture-of-Datatype LLM Accelerationcited by 18
- 2024Enabling Unstructured Sparse Acceleration on Structured Sparse Acceleratorscited by 8
- 2024Towards Efficient Neuro-Symbolic AI: From Workload Characterization to Hardware Architecturecited by 7
- 2024SDQ: Sparse Decomposed Quantization for LLM Inferencecited by 4
- 2025MCBP: A Memory-Compute Efficient LLM Inference Accelerator Leveraging Bit-Slice-enabled Sparsity and Repetitivenesscited by 4
- 2024BBS: Bi-directional Bit-level Sparsity for Deep Learning Accelerationcited by 3
- 2025Accelerating LLM Inference with Flexible N:M Sparsity via A Fully Digital Compute-in-Memory Acceleratorcited by 3
- 2024Torch2Chip: An End-to-end Customizable Deep Neural Network Compression and Deployment Toolkit for Prototype Hardware Accelerator Designcited by 1
- 2024Toward Efficient Permutation for Hierarchical N:M Sparsity on GPUscited by 0
- 2025TriADA: Massively Parallel Trilinear Matrix-by-Tensor Multiply-Add Algorithm and Device Architecture for the Acceleration of 3D Discrete Transformationscited by 0
- 2026GPU Acceleration of Sparse Fully Homomorphic Encrypted DNNscited by 0
- 2026Kaleido: Algorithm-Hardware Co-Design for Video Diffusion Transformers by Exploiting Latent Space Correlationscited by 0
- 2026Kaleido: Algorithm-Hardware Co-Design for Video Diffusion Transformers by Exploiting Latent Space Correlations15 Jul 2026
- 2026GPU Acceleration of Sparse Fully Homomorphic Encrypted DNNs13 Apr 2026
- 2025MCBP: A Memory-Compute Efficient LLM Inference Accelerator Leveraging Bit-Slice-enabled Sparsity and Repetitiveness12 Sep 2025
- 2025TriADA: Massively Parallel Trilinear Matrix-by-Tensor Multiply-Add Algorithm and Device Architecture for the Acceleration of 3D Discrete Transformations28 Jun 2025
- 2025Accelerating LLM Inference with Flexible N:M Sparsity via A Fully Digital Compute-in-Memory Accelerator19 Apr 2025
- 2024BitMoD: Bit-serial Mixture-of-Datatype LLM Acceleration18 Nov 2024
- 2024Towards Efficient Neuro-Symbolic AI: From Workload Characterization to Hardware Architecture20 Sep 2024
- 2024BBS: Bi-directional Bit-level Sparsity for Deep Learning Acceleration8 Sep 2024
- 2024Toward Efficient Permutation for Hierarchical N:M Sparsity on GPUs30 Jul 2024
- 2024SDQ: Sparse Decomposed Quantization for LLM Inference19 Jun 2024
- 2024Torch2Chip: An End-to-end Customizable Deep Neural Network Compression and Deployment Toolkit for Prototype Hardware Accelerator Design2 May 2024
- 2024Enabling Unstructured Sparse Acceleration on Structured Sparse Accelerators12 Mar 2024