GRANITE: A Graph Neural Network Model for Basic Block Throughput Estimation
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Abstract (arXiv)
Analytical hardware performance models yield swift estimation of desired hardware performance metrics. However, developing these analytical models for modern processors with sophisticated microarchitectures is an extremely laborious task and requires a firm understanding of target microarchitecture's internal structure. In this paper, we introduce GRANITE, a new machine learning model that estimates the throughput of basic blocks across different microarchitectures. GRANITE uses a graph representation of basic blocks that captures both structural and data dependencies between instructions. This representation is processed using a graph neural network that takes advantage of the relational information captured in the graph and learns a rich neural representation of the basic block that allows more precise throughput estimation. Our results establish a new state-of-the-art for basic block performance estimation with an average test error of 6.9% across a wide range of basic blocks and microarchitectures for the x86-64 target. Compared to recent work, this reduced the error by 1.7% while improving training and inference throughput by approximately 3.0x. In addition, we propose the use of multi-task learning with independent multi-layer feed forward decoder networks. Our results show that this technique further improves precision of all learned models while significantly reducing per-microarchitecture training costs. We perform an extensive set of ablation studies and comparisons with prior work, concluding a set of methods to achieve high accuracy for basic block performance estimation.
Key facts. Cited by 9 papers in the map (data through 14 Oct 2026). Builds on 31 of its 72 references that are in the map. First posted on arXiv 8 Oct 2022.
Builds on
31 of 72 references.
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Citing papers per year: 2022: 1; 2023: 4; 2024: 3; 2025: 0; 2026: 1.
9 papers.
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- 2023ArchGym: An Open-Source Gymnasium for Machine Learning Assisted Architecture Designcited by 6
- 2022Application Performance Modeling via Tensor Completioncited by 3
- 2024Tao: Re-Thinking DL-based Microarchitecture Simulationcited by 3
- 2023Learning Generalizable Program and Architecture Representations for Performance Modelingcited by 2
- 2023COMET: Neural Cost Model Explanation Frameworkcited by 1
- 2024A Benchmark on Directed Graph Representation Learning in Hardware Designscited by 1
- 2026On the Limits of Machine-Learned Ranking for Modern Microarchitectural Policiescited by 0
- 2026On the Limits of Machine-Learned Ranking for Modern Microarchitectural Policies2 Aug 2026
- 2024LayerDAG: A Layerwise Autoregressive Diffusion Model for Directed Acyclic Graph Generation4 Nov 2024
- 2024A Benchmark on Directed Graph Representation Learning in Hardware Designs9 Oct 2024
- 2024Tao: Re-Thinking DL-based Microarchitecture Simulation16 Apr 2024
- 2023Learning Generalizable Program and Architecture Representations for Performance Modeling25 Oct 2023
- 2023TpuGraphs: A Performance Prediction Dataset on Large Tensor Computational Graphs25 Aug 2023
- 2023ArchGym: An Open-Source Gymnasium for Machine Learning Assisted Architecture Design15 Jun 2023
- 2023COMET: Neural Cost Model Explanation Framework14 Feb 2023
- 2022Application Performance Modeling via Tensor Completion18 Oct 2022