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Experts in the Loop: Conditional Variable Selection for Accelerating Post-Silicon Analysis Based on Deep Learning

arXiv 2209.15249 ↗First posted 30 Sep 2022cs.LGcited by 0

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Abstract (arXiv)

Post-silicon validation is one of the most critical processes in modern semiconductor manufacturing. Specifically, correct and deep understanding in test cases of manufactured devices is key to enable post-silicon tuning and debugging. This analysis is typically performed by experienced human experts. However, with the fast development in semiconductor industry, test cases can contain hundreds of variables. The resulting high-dimensionality poses enormous challenges to experts. Thereby, some recent prior works have introduced data-driven variable selection algorithms to tackle these problems and achieved notable success. Nevertheless, for these methods, experts are not involved in training and inference phases, which may lead to bias and inaccuracy due to the lack of prior knowledge. Hence, this work for the first time aims to design a novel conditional variable selection approach while keeping experts in the loop. In this way, we expect that our algorithm can be more efficiently and effectively trained to identify the most critical variables under certain expert knowledge. Extensive experiments on both synthetic and real-world datasets from industry have been conducted and shown the effectiveness of our method.

Key facts. No citing papers in the map yet (data through 7 Oct 2026). Builds on 7 of its 21 references that are in the map. First posted on arXiv 30 Sep 2022.

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References · 7

  1. 2014Adam: A Method for Stochastic Optimizationcited by 36,960
  2. 2019Concrete Autoencoders for Differentiable Feature Selection and Reconstructioncited by 90
  3. 2019AFS: An Attention-based mechanism for Supervised Feature Selectioncited by 21
  4. 2020Feature Selection Using Batch-Wise Attenuation and Feature Mask Normalizationcited by 11
  5. 2021Self-Learning Tuning for Post-Silicon Validationcited by 2
  6. 2022A Deep-Learning-Aided Pipeline for Efficient Post-Silicon Tuningcited by 2
  7. 2017Design-Phase Buffer Allocation for Post-Silicon Clock Binning by Iterative Learningcited by 1

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