Self-Learning Tuning for Post-Silicon Validation
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Abstract (arXiv)
Increasing complexity of modern chips makes design validation more difficult. Existing approaches are not able anymore to cope with the complexity of tasks such as robust performance tuning in post-silicon validation. Therefore, we propose a novel approach based on learn-to-optimize and reinforcement learning in order to solve complex and mixed-type tuning tasks in a efficient and robust way.
Key facts. Cited by 2 papers in the map (data through 7 Oct 2026). Builds on 14 of its 37 references that are in the map. First posted on arXiv 17 Nov 2021.
Builds on
14 of 37 references.
References · 14
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- 2019Optuna: A Next-generation Hyperparameter Optimization Frameworkcited by 2,455
- 2016Neural Architecture Search with Reinforcement Learningcited by 1,489
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- 2017Learning Combinatorial Optimization Algorithms over Graphscited by 557
- 2018Tune: A Research Platform for Distributed Model Selection and Trainingcited by 395
- 2017Deep Reinforcement Learning: An Overviewcited by 327
- 2019Simple Black-box Adversarial Attackscited by 249
- 2021Learning to Optimize: A Primer and A Benchmarkcited by 206
- 2018An Introduction to Deep Reinforcement Learningcited by 201
- 2016Learning to Optimizecited by 195
- 2017Learned Optimizers that Scale and Generalizecited by 109
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Citing papers per year: 2022: 2.
2 papers.