mlsanityData to 13 Oct 2026

RobustAnalog: Fast Variation-Aware Analog Circuit Design Via Multi-task RL

arXiv 2207.06412 ↗First posted 13 Jul 2022cs.ET cs.AI cs.LGcited by 5

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Abstract (arXiv)

Analog/mixed-signal circuit design is one of the most complex and time-consuming stages in the whole chip design process. Due to various process, voltage, and temperature (PVT) variations from chip manufacturing, analog circuits inevitably suffer from performance degradation. Although there has been plenty of work on automating analog circuit design under the typical condition, limited research has been done on exploring robust designs under real and unpredictable silicon variations. Automatic analog design against variations requires prohibitive computation and time costs. To address the challenge, we present RobustAnalog, a robust circuit design framework that involves the variation information in the optimization process. Specifically, circuit optimizations under different variations are considered as a set of tasks. Similarities among tasks are leveraged and competitions are alleviated to realize a sample-efficient multi-task training. Moreover, RobustAnalog prunes the task space according to the current performance in each iteration, leading to a further simulation cost reduction. In this way, RobustAnalog can rapidly produce a set of circuit parameters that satisfies diverse constraints (e.g. gain, bandwidth, noise...) across variations. We compare RobustAnalog with Bayesian optimization, Evolutionary algorithm, and Deep Deterministic Policy Gradient (DDPG) and demonstrate that RobustAnalog can significantly reduce required optimization time by 14-30 times. Therefore, our study provides a feasible method to handle various real silicon conditions.

Key facts. Cited by 5 papers in the map (data through 13 Oct 2026). Builds on 18 of its 38 references that are in the map. First posted on arXiv 13 Jul 2022.

Builds on

18 of 38 references.

References · 18

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6 more
  1. 2020AutoCkt: Deep Reinforcement Learning of Analog Circuit Designscited by 51
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Cited by year (2026 to 13 Oct)

Citing papers per year: 2025: 4; 2026: 1.

5 papers.

  1. 2025AnaFlow: Agentic LLM-based Workflow for Reasoning-Driven Explainable and Sample-Efficient Analog Circuit Sizingcited by 10
  2. 2025HeaRT: A Hierarchical Circuit Reasoning Tree-Based Agentic Framework for AMS Design Optimizationcited by 5
  3. 2025GLOVA: Global and Local Variation-Aware Analog Circuit Design with Risk-Sensitive Reinforcement Learningcited by 1
  4. 2025Emerging ML-AI Techniques for Analog and RF EDAcited by 1
  5. 2026Lighthouse RL: Sample-Efficient Circuit Optimization via Strategic Reset Pointscited by 0