A Design Methodology for Fault-Tolerant Computing using Astrocyte Neural Networks
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Abstract (arXiv)
We propose a design methodology to facilitate fault tolerance of deep learning models. First, we implement a many-core fault-tolerant neuromorphic hardware design, where neuron and synapse circuitries in each neuromorphic core are enclosed with astrocyte circuitries, the star-shaped glial cells of the brain that facilitate self-repair by restoring the spike firing frequency of a failed neuron using a closed-loop retrograde feedback signal. Next, we introduce astrocytes in a deep learning model to achieve the required degree of tolerance to hardware faults. Finally, we use a system software to partition the astrocyte-enabled model into clusters and implement them on the proposed fault-tolerant neuromorphic design. We evaluate this design methodology using seven deep learning inference models and show that it is both area and power efficient.
Key facts. Cited by 4 papers in the map (data through 14 Oct 2026). First posted on arXiv 6 Apr 2022.
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Citing papers per year: 2023: 1; 2024: 3.
4 papers.
- 2023Exploiting FPGA Capabilities for Accelerated Biomedical Computingcited by 2
- 2024NEUROSEC: FPGA-Based Neuromorphic Audio Securitycited by 2
- 2024Advancing Neuromorphic Computing: Mixed-Signal Design Techniques Leveraging Brain Code Units and Fundamental Code Unitscited by 0
- 2024HPCNeuroNet: A Neuromorphic Approach Merging SNN Temporal Dynamics with Transformer Attention for FPGA-based Particle Physicscited by 0
- 2024HPCNeuroNet: A Neuromorphic Approach Merging SNN Temporal Dynamics with Transformer Attention for FPGA-based Particle Physics23 Dec 2024
- 2024Advancing Neuromorphic Computing: Mixed-Signal Design Techniques Leveraging Brain Code Units and Fundamental Code Units18 Mar 2024
- 2024NEUROSEC: FPGA-Based Neuromorphic Audio Security22 Jan 2024
- 2023Exploiting FPGA Capabilities for Accelerated Biomedical Computing16 Jul 2023