Learning Intermediate Representations using Graph Neural Networks for NUMA and Prefetchers Optimization
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Abstract (arXiv)
There is a large space of NUMA and hardware prefetcher configurations that can significantly impact the performance of an application. Previous studies have demonstrated how a model can automatically select configurations based on the dynamic properties of the code to achieve speedups. This paper demonstrates how the static Intermediate Representation (IR) of the code can guide NUMA/prefetcher optimizations without the prohibitive cost of performance profiling. We propose a method to create a comprehensive dataset that includes a diverse set of intermediate representations along with optimum configurations. We then apply a graph neural network model in order to validate this dataset. We show that our static intermediate representation based model achieves 80% of the performance gains provided by expensive dynamic performance profiling based strategies. We further develop a hybrid model that uses both static and dynamic information. Our hybrid model achieves the same gains as the dynamic models but at a reduced cost by only profiling 30% of the programs.
Key facts. Cited by 9 papers in the map (data through 7 Oct 2026). Builds on 12 of its 59 references that are in the map. First posted on arXiv 1 Mar 2022.
Builds on
12 of 59 references.
References · 12
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Built on by
Citing papers per year: 2022: 1; 2023: 5; 2024: 2; 2025: 0; 2026: 1.
9 papers.
- 2024The Landscape and Challenges of HPC Research and LLMscited by 22
- 2023Learning to Parallelize with OpenMP by Augmented Heterogeneous AST Representationcited by 14
- 2023Performance Optimization using Multimodal Modeling and Heterogeneous GNNcited by 7
- 2023AutoParLLM: GNN-guided Context Generation for Zero-Shot Code Parallelization using LLMscited by 5
- 2022Heterogeneous Graph Neural Networks for Software Effort Estimationcited by 3
- 2023PERFOGRAPH: A Numerical Aware Program Graph Representation for Performance Optimization and Program Analysiscited by 3
- 2023Power Constrained Autotuning using Graph Neural Networkscited by 2
- 2024MIREncoder: Multi-modal IR-based Pretrained Embeddings for Performance Optimizationscited by 2
- 2026Accelerating Transfer-Learning-Based Autotuning with Predictive LLVM IR Performance Rankingcited by 0
- 2026Accelerating Transfer-Learning-Based Autotuning with Predictive LLVM IR Performance Ranking14 Sep 2026
- 2024MIREncoder: Multi-modal IR-based Pretrained Embeddings for Performance Optimizations2 Jul 2024
- 2024The Landscape and Challenges of HPC Research and LLMs3 Feb 2024
- 2023AutoParLLM: GNN-guided Context Generation for Zero-Shot Code Parallelization using LLMs6 Oct 2023
- 2023PERFOGRAPH: A Numerical Aware Program Graph Representation for Performance Optimization and Program Analysis31 May 2023
- 2023Learning to Parallelize with OpenMP by Augmented Heterogeneous AST Representation9 May 2023
- 2023Performance Optimization using Multimodal Modeling and Heterogeneous GNN25 Apr 2023
- 2023Power Constrained Autotuning using Graph Neural Networks22 Feb 2023
- 2022Heterogeneous Graph Neural Networks for Software Effort Estimation22 Jun 2022