Enabling Automated FPGA Accelerator Optimization Using Graph Neural Networks
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Abstract (arXiv)
High-level synthesis (HLS) has freed the computer architects from developing their designs in a very low-level language and needing to exactly specify how the data should be transferred in register-level. With the help of HLS, the hardware designers must describe only a high-level behavioral flow of the design. Despite this, it still can take weeks to develop a high-performance architecture mainly because there are many design choices at a higher level that requires more time to explore. It also takes several minutes to hours to get feedback from the HLS tool on the quality of each design candidate. In this paper, we propose to solve this problem by modeling the HLS tool with a graph neural network (GNN) that is trained to be used for a wide range of applications. The experimental results demonstrate that by employing the GNN-based model, we are able to estimate the quality of design in milliseconds with high accuracy which can help us search through the solution space very quickly.
Key facts. No citing papers in the map yet (data through 14 Oct 2026). Builds on 17 of its 47 references that are in the map. First posted on arXiv 17 Nov 2021.
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17 of 47 references.
References · 17
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5 more
- 2020AutoDNNchip: An Automated DNN Chip Predictor and Builder for Both FPGAs and ASICscited by 26
- 2021IronMan: GNN-assisted Design Space Exploration in High-Level Synthesis via Reinforcement Learningcited by 26
- 2020AutoDSE: Enabling Software Programmers to Design Efficient FPGA Acceleratorscited by 25
- 2018AutoAccel: Automated Accelerator Generation and Optimization with Composable, Parallel and Pipeline Architecturecited by 5
- 2020Predictable Accelerator Design with Time-Sensitive Affine Typescited by 4
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