Multiplierless MP-Kernel Machine For Energy-efficient Edge Devices
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Abstract (arXiv)
We present a novel framework for designing multiplierless kernel machines that can be used on resource-constrained platforms like intelligent edge devices. The framework uses a piecewise linear (PWL) approximation based on a margin propagation (MP) technique and uses only addition/subtraction, shift, comparison, and register underflow/overflow operations. We propose a hardware-friendly MP-based inference and online training algorithm that has been optimized for a Field Programmable Gate Array (FPGA) platform. Our FPGA implementation eliminates the need for DSP units and reduces the number of LUTs. By reusing the same hardware for inference and training, we show that the platform can overcome classification errors and local minima artifacts that result from the MP approximation. The implementation of this proposed multiplierless MP-kernel machine on FPGA results in an estimated energy consumption of 13.4 pJ and power consumption of 107 mW with ~9k LUTs and FFs each for a 256 x 32 sized kernel making it superior in terms of power, performance, and area compared to other comparable implementations.
Key facts. Cited by 4 papers in the map (data through 14 Oct 2026). Builds on 12 of its 56 references that are in the map. First posted on arXiv 3 Jun 2021.
Builds on
12 of 56 references.
References · 12
- 2015Deep Compression: Compressing Deep Neural Networks with Pruning, Trained Quantization and Huffman Codingcited by 2,329
- 2016XNOR-Net: ImageNet Classification Using Binary Convolutional Neural Networkscited by 849
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- 2019HAWQ: Hessian AWare Quantization of Neural Networks with Mixed-Precisioncited by 402
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- 2019AdderNet: Do We Really Need Multiplications in Deep Learning?cited by 82
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- 2019DeepShift: Towards Multiplication-Less Neural Networkscited by 54
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- 2018A Highly Parallel FPGA Implementation of Sparse Neural Network Trainingcited by 4
- 2020A Review of Recent Advances of Binary Neural Networks for Edge Computingcited by 3
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Citing papers per year: 2022: 2; 2023: 2.
4 papers.
- 2022Bias-Scalable Near-Memory CMOS Analog Processor for Machine Learningcited by 2
- 2022Process, Bias and Temperature Scalable CMOS Analog Computing Circuits for Machine Learningcited by 1
- 2023A Framework for Analyzing Cross-correlators using Price's Theorem and Piecewise-Linear Decompositioncited by 0
- 2023Multiplierless In-filter Computing for tinyML Platformscited by 0
- 2023Multiplierless In-filter Computing for tinyML Platforms24 Apr 2023
- 2023A Framework for Analyzing Cross-correlators using Price's Theorem and Piecewise-Linear Decomposition18 Apr 2023
- 2022Process, Bias and Temperature Scalable CMOS Analog Computing Circuits for Machine Learning11 May 2022
- 2022Bias-Scalable Near-Memory CMOS Analog Processor for Machine Learning10 Feb 2022