ANNETTE: Accurate Neural Network Execution Time Estimation with Stacked Models
Not on the map. Why?
Abstract (arXiv)
With new accelerator hardware for DNN, the computing power for AI applications has increased rapidly. However, as DNN algorithms become more complex and optimized for specific applications, latency requirements remain challenging, and it is critical to find the optimal points in the design space. To decouple the architectural search from the target hardware, we propose a time estimation framework that allows for modeling the inference latency of DNNs on hardware accelerators based on mapping and layer-wise estimation models. The proposed methodology extracts a set of models from micro-kernel and multi-layer benchmarks and generates a stacked model for mapping and network execution time estimation. We compare estimation accuracy and fidelity of the generated mixed models, statistical models with the roofline model, and a refined roofline model for evaluation. We test the mixed models on the ZCU102 SoC board with DNNDK and Intel Neural Compute Stick 2 on a set of 12 state-of-the-art neural networks. It shows an average estimation error of 3.47% for the DNNDK and 7.44% for the NCS2, outperforming the statistical and analytical layer models for almost all selected networks. For a randomly selected subset of 34 networks of the NASBench dataset, the mixed model reaches fidelity of 0.988 in Spearman's rank correlation coefficient metric. The code of ANNETTE is publicly available at https://github.com/embedded-machine-learning/annette.
Key facts. Cited by 1 paper in the map (data through 7 Oct 2026). Builds on 18 of its 37 references that are in the map. First posted on arXiv 7 May 2021.
Builds on
18 of 37 references.
References · 18
- 2018MobileNetV2: Inverted Residuals and Linear Bottleneckscited by 4,773
- 2017ShuffleNet: An Extremely Efficient Convolutional Neural Network for Mobile Devicescited by 1,194
- 2018ProxylessNAS: Direct Neural Architecture Search on Target Task and Hardwarecited by 666
- 2018FBNet: Hardware-Aware Efficient ConvNet Design via Differentiable Neural Architecture Searchcited by 480
- 2019NAS-Bench-101: Towards Reproducible Neural Architecture Searchcited by 340
- 2014Speeding up Convolutional Neural Networks with Low Rank Expansionscited by 283
- 2019MLPerf Inference Benchmarkcited by 195
- 2018NetAdapt: Platform-Aware Neural Network Adaptation for Mobile Applicationscited by 146
- 2015Data-free parameter pruning for Deep Neural Networkscited by 112
- 2015Convolutional neural networks with low-rank regularizationcited by 102
- 2016Convolutional Neural Networks using Logarithmic Data Representationcited by 97
- 2017Cardiologist-Level Arrhythmia Detection with Convolutional Neural Networkscited by 52
6 more
- 2020FBNetV3: Joint Architecture-Recipe Search using Predictor Pretrainingcited by 35
- 2019SqueezeNAS: Fast neural architecture search for faster semantic segmentationcited by 31
- 2017NeuralPower: Predict and Deploy Energy-Efficient Convolutional Neural Networkscited by 30
- 2020DNN-Chip Predictor: An Analytical Performance Predictor for DNN Accelerators with Various Dataflows and Hardware Architecturescited by 16
- 2015Fixed-Point Performance Analysis of Recurrent Neural Networkscited by 10
- 2019PreVIous: A Methodology for Prediction of Visual Inference Performance on IoT Devicescited by 2
Built on by
Citing papers per year: 2024: 1.
1 paper.