unzipFPGA: Enhancing FPGA-based CNN Engines with On-the-Fly Weights Generation
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Abstract (arXiv)
Single computation engines have become a popular design choice for FPGA-based convolutional neural networks (CNNs) enabling the deployment of diverse models without fabric reconfiguration. This flexibility, however, often comes with significantly reduced performance on memory-bound layers and resource underutilisation due to suboptimal mapping of certain layers on the engine's fixed configuration. In this work, we investigate the implications in terms of CNN engine design for a class of models that introduce a pre-convolution stage to decompress the weights at run time. We refer to these approaches as on-the-fly. To minimise the negative impact of limited bandwidth on memory-bound layers, we present a novel hardware component that enables the on-chip on-the-fly generation of weights. We further introduce an input selective processing element (PE) design that balances the load between PEs on suboptimally mapped layers. Finally, we present unzipFPGA, a framework to train on-the-fly models and traverse the design space to select the highest performing CNN engine configuration. Quantitative evaluation shows that unzipFPGA yields an average speedup of 2.14x and 71% over optimised status-quo and pruned CNN engines under constrained bandwidth and up to 3.69x higher performance density over the state-of-the-art FPGA-based CNN accelerators.
Key facts. Cited by 4 papers in the map (data through 7 Oct 2026). Builds on 38 of its 87 references that are in the map. First posted on arXiv 9 Mar 2021.
Builds on
38 of 87 references.
References · 38
- 2015Deep Residual Learning for Image Recognitioncited by 51,809
- 2014Adam: A Method for Stochastic Optimizationcited by 36,960
- 2019PyTorch: An Imperative Style, High-Performance Deep Learning Librarycited by 20,160
- 2015Deep Compression: Compressing Deep Neural Networks with Pruning, Trained Quantization and Huffman Codingcited by 2,291
- 2017Quantization and Training of Neural Networks for Efficient Integer-Arithmetic-Only Inferencecited by 1,548
- 2016SqueezeNet: AlexNet-level accuracy with 50x fewer parameters and <0.5MB model sizecited by 1,054
- 2016HyperNetworkscited by 1,003
- 2020What is the State of Neural Network Pruning?cited by 578
- 2016Learning Structured Sparsity in Deep Neural Networkscited by 538
- 2019Importance Estimation for Neural Network Pruningcited by 531
- 2018Quantizing deep convolutional networks for efficient inference: A whitepapercited by 507
- 2017ThiNet: A Filter Level Pruning Method for Deep Neural Network Compressioncited by 438
26 more
- 2019HAWQ: Hessian AWare Quantization of Neural Networks with Mixed-Precisioncited by 387
- 2018Soft Filter Pruning for Accelerating Deep Convolutional Neural Networkscited by 313
- 2016EIE: Efficient Inference Engine on Compressed Deep Neural Networkcited by 291
- 2016FINN: A Framework for Fast, Scalable Binarized Neural Network Inferencecited by 141
- 2020Sparse GPU Kernels for Deep Learningcited by 138
- 2017SCNN: An Accelerator for Compressed-sparse Convolutional Neural Networkscited by 132
- 2020APQ: Joint Search for Network Architecture, Pruning and Quantization Policycited by 98
- 2020LogicNets: Co-Designed Neural Networks and Circuits for Extreme-Throughput Applicationscited by 55
- 2018FINN-R: An End-to-End Deep-Learning Framework for Fast Exploration of Quantized Neural Networkscited by 54
- 2017CirCNN: Accelerating and Compressing Deep Neural Networks Using Block-CirculantWeight Matricescited by 53
- 2020Co-Exploration of Neural Architectures and Heterogeneous ASIC Accelerator Designs Targeting Multiple Taskscited by 43
- 2016Bit-pragmatic Deep Neural Network Computingcited by 30
- 2020Best of Both Worlds: AutoML Codesign of a CNN and its Hardware Acceleratorcited by 30
- 2016Maximizing CNN Accelerator Efficiency Through Resource Partitioningcited by 29
- 2018Toolflows for Mapping Convolutional Neural Networks on FPGAs: A Survey and Future Directionscited by 27
- 2018DCFNet: Deep Neural Network with Decomposed Convolutional Filterscited by 23
- 2019LUTNet: Learning FPGA Configurations for Highly Efficient Neural Network Inferencecited by 23
- 2018DLA: Compiler and FPGA Overlay for Neural Network Inference Accelerationcited by 13
- 2020PERMDNN: Efficient Compressed DNN Architecture with Permuted Diagonal Matricescited by 12
- 2017An OpenCL(TM) Deep Learning Accelerator on Arria 10cited by 11
- 2020Searching for Winograd-aware Quantized Networkscited by 11
- 2018f-CNNx: A Toolflow for Mapping Multi-CNN Applications on FPGAscited by 6
- 2019DNNVM : End-to-End Compiler Leveraging Heterogeneous Optimizations on FPGA-based CNN Acceleratorscited by 6
- 2019FSNet: Compression of Deep Convolutional Neural Networks by Filter Summarycited by 5
- 2019Automatic Generation of Multi-precision Multi-arithmetic CNN Accelerators for FPGAscited by 5
- 2017Compiling Deep Learning Models for Custom Hardware Acceleratorscited by 3
Built on by
Citing papers per year: 2021: 1; 2022: 2; 2023: 1.
4 papers.
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- 2022Multi-DNN Accelerators for Next-Generation AI Systems19 May 2022
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