Mobile Machine Learning Hardware at ARM: A Systems-on-Chip (SoC) Perspective
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Abstract (arXiv)
Machine learning is playing an increasingly significant role in emerging mobile application domains such as AR/VR, ADAS, etc. Accordingly, hardware architects have designed customized hardware for machine learning algorithms, especially neural networks, to improve compute efficiency. However, machine learning is typically just one processing stage in complex end-to-end applications, involving multiple components in a mobile Systems-on-a-chip (SoC). Focusing only on ML accelerators loses bigger optimization opportunity at the system (SoC) level. This paper argues that hardware architects should expand the optimization scope to the entire SoC. We demonstrate one particular case-study in the domain of continuous computer vision where camera sensor, image signal processor (ISP), memory, and NN accelerator are synergistically co-designed to achieve optimal system-level efficiency.
Key facts. Cited by 3 papers in the map (data through 7 Oct 2026). First posted on arXiv 19 Jan 2018.
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Citing papers per year: 2021: 3.
3 papers.
- 2021S2TA: Exploiting Structured Sparsity for Energy-Efficient Mobile CNN Accelerationcited by 19
- 2021Doping: A technique for efficient compression of LSTM models using sparse structured additive matricescited by 5
- 2021TinyML: Analysis of Xtensa LX6 microprocessor for Neural Network Applications by ESP32 SoCcited by 0
- 2021S2TA: Exploiting Structured Sparsity for Energy-Efficient Mobile CNN Acceleration16 Jul 2021
- 2021TinyML: Analysis of Xtensa LX6 microprocessor for Neural Network Applications by ESP32 SoC20 Jun 2021
- 2021Doping: A technique for efficient compression of LSTM models using sparse structured additive matrices14 Feb 2021