A Transprecision Floating-Point Platform for Ultra-Low Power Computing
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Abstract (arXiv)
In modern low-power embedded platforms, floating-point (FP) operations emerge as a major contributor to the energy consumption of compute-intensive applications with large dynamic range. Experimental evidence shows that 50% of the energy consumed by a core and its data memory is related to FP computations. The adoption of FP formats requiring a lower number of bits is an interesting opportunity to reduce energy consumption, since it allows to simplify the arithmetic circuitry and to reduce the memory bandwidth between memory and registers by enabling vectorization. From a theoretical point of view, the adoption of multiple FP types perfectly fits with the principle of transprecision computing, allowing fine-grained control of approximation while meeting specified constraints on the precision of final results. In this paper we propose an extended FP type system with complete hardware support to enable transprecision computing on low-power embedded processors, including two standard formats (binary32 and binary16) and two new formats (binary8 and binary16alt). First, we introduce a software library that enables exploration of FP types by tuning both precision and dynamic range of program variables. Then, we present a methodology to integrate our library with an external tool for precision tuning, and experimental results that highlight the clear benefits of introducing the new formats. Finally, we present the design of a transprecision FP unit capable of handling 8-bit and 16-bit operations in addition to standard 32-bit operations. Experimental results on FP-intensive benchmarks show that up to 90% of FP operations can be safely scaled down to 8-bit or 16-bit formats. Thanks to precision tuning and vectorization, execution time is decreased by 12% and memory accesses are reduced by 27% on average, leading to a reduction of energy consumption up to 30%.
Key facts. Cited by 5 papers in the map (data through 14 Oct 2026). First posted on arXiv 28 Nov 2017.
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Citing papers per year: 2021: 2; 2022: 0; 2023: 2; 2024: 0; 2025: 1.
5 papers.
- 2021PRECODE - A Generic Model Extension to Prevent Deep Gradient Leakagecited by 28
- 2025Enhancing Large Language Models for Hardware Verification: A Novel SystemVerilog Assertion Datasetcited by 10
- 2023RedMule: A Mixed-Precision Matrix-Matrix Operation Engine for Flexible and Energy-Efficient On-Chip Linear Algebra and TinyML Training Accelerationcited by 4
- 2021A matrix math facility for Power ISA(TM) processorscited by 3
- 2023Multiplierless In-filter Computing for tinyML Platformscited by 0
- 2025Enhancing Large Language Models for Hardware Verification: A Novel SystemVerilog Assertion Dataset11 Mar 2025
- 2023Multiplierless In-filter Computing for tinyML Platforms24 Apr 2023
- 2023RedMule: A Mixed-Precision Matrix-Matrix Operation Engine for Flexible and Energy-Efficient On-Chip Linear Algebra and TinyML Training Acceleration10 Jan 2023
- 2021PRECODE - A Generic Model Extension to Prevent Deep Gradient Leakage10 Aug 2021
- 2021A matrix math facility for Power ISA(TM) processors7 Apr 2021