Design-Time Optimization of Deep Neural Networks for Intermittent Learning on Microcontrollers
Not on the map. Why?
Abstract (arXiv)
We present a method for designing deep neural networks (DNNs) for intermittent, energy-autonomous, on-device learning on microcontroller units (MCUs). In mobile applications where the energy can run out, e.g., when solar-powered, executing artificial intelligence (AI) faces a technical issue as learning can be interrupted at any time. Our approach combines a hardware-aware energy prediction model with multi-objective optimization (MOO), enabling offline DNN optimization at the design stage without repeated deployment and online testing on the target MCU. Our proposed energy predictor estimates per-layer energy consumption for both DNN inference and training, including the intermittent checkpointing overhead, based on implementation-specific compute and memory features extracted from the DNN model. We validate our approach using autoencoders for anomaly detection on a Cortex-M4 MCU, where our predictor achieves a weighted absolute percentage error of 16.6%, which is sufficient for reliable architecture selection under intermittency constraints. As a result, this work bridges the gap between MOO, automated DNN design, deployment on energy-harvesting systems, and intermittent learning, truly enabling autonomous AI at the edge.
Key facts. No citing papers in the map yet (data through 7 Oct 2026). Builds on 5 of its 21 references that are in the map. First posted on arXiv 4 Aug 2026.
Builds on
5 of 21 references.
References · 5
- 2022On-Device Training Under 256KB Memorycited by 158
- 2021TinyOL: TinyML with Online-Learning on Microcontrollerscited by 65
- 2022Energy Consumption of Neural Networks on NVIDIA Edge Boards: an Empirical Modelcited by 7
- 2024MicroNAS: Zero-Shot Neural Architecture Search for MCUscited by 5
- 2024On-Device Training of Fully Quantized Deep Neural Networks on Cortex-M Microcontrollerscited by 5
Built on by
Not cited yet.