Hardware Efficient Approximate Convolution with Tunable Error Tolerance for CNNs
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Abstract (arXiv)
Modern CNNs' high computational demands hinder edge deployment, as traditional ``hard'' sparsity (skipping mathematical zeros) loses effectiveness in deep layers or with smooth activations like Tanh. We propose a ``soft sparsity'' paradigm using a hardware efficient Most Significant Bit (MSB) proxy to skip negligible non-zero multiplications. Integrated as a custom RISC-V instruction and evaluated on LeNet-5 (MNIST), this method reduces ReLU MACs by 88.42% and Tanh MACs by 74.87% with zero accuracy loss--outperforming zero-skipping by 5x. By clock-gating inactive multipliers, we estimate power savings of 35.2% for ReLU and 29.96% for Tanh. While memory access makes power reduction sub-linear to operation savings, this approach significantly optimizes resource-constrained inference.
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References · 7
- 2015Deep Residual Learning for Image Recognitioncited by 52,096
- 2014Going Deeper with Convolutionscited by 4,241
- 2016EIE: Efficient Inference Engine on Compressed Deep Neural Networkcited by 295
- 2021Accelerating Sparse Deep Neural Networkscited by 223
- 2020The Hardware Lotterycited by 160
- 2017NullHop: A Flexible Convolutional Neural Network Accelerator Based on Sparse Representations of Feature Mapscited by 39
- 2016Bit-pragmatic Deep Neural Network Computingcited by 32
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