SkyEgg: Heterogeneity-Aware Hardware Synthesis via Equality Saturation

Hardware synthesis is a key interface between high-level programs and accelerator designs. Modern FPGAs increasingly expose heterogeneity in resource functionality and timing configurability. Exploiting these resources requires synthesis to choose among hardware implementations and fine-grained configuration options, and coordinate these choices across multiple stages. However, prior frameworks fail to fully explore these choices due to resource models confined to per-operation mappings and limited fusion patterns. Moreover, they perform transformation, scheduling, and mapping sequentially, selecting an expression form and assigning cycle boundaries before full mapping information is available. This problem precludes chaining and fusion, excludes viable implementations from subsequent optimization stages, and limits end-to-end performance. We present SkyEgg, a heterogeneity-aware hardware synthesis framework for FPGAs. The key insight of SkyEgg is to bring algebraic equivalence and diverse resource capabilities together throughout the synthesis flow. Specifically, it encodes target-specific hardware mappings and configurations as extensible mapping rules alongside algebraic rewrite rules in equality saturation, placing algebraic and resource alternatives in a common representation. It further proposes transformation- and mapping-aware scheduling that uses these alternatives and configuration-specific timing to jointly select an equivalent form, its resource mappings, and cycle assignments to minimize end-to-end latency under target-frequency and hardware constraints. This algebraic exploration reveals forms that enable otherwise unavailable mappings. SkyEgg also provides a heuristic solver that rapidly finds high-quality solutions. Against two commercial HLS tools, SkyEgg achieves average speedups of 3.12x over Vitis HLS and 3.18x over Altera HLS across target frequencies.