mlsanityData to 14 Oct 2026

An ultra-low-power CGRA for accelerating Transformers at the edge

arXiv 2507.12904 ↗First posted 17 Jul 2025cs.AR cs.AIcited by 0

Not on the map. Why?

Abstract (arXiv)

Transformers have revolutionized deep learning with applications in natural language processing, computer vision, and beyond. However, their computational demands make it challenging to deploy them on low-power edge devices. This paper introduces an ultra-low-power, Coarse-Grained Reconfigurable Array (CGRA) architecture specifically designed to accelerate General Matrix Multiplication (GEMM) operations in transformer models tailored for the energy and resource constraints of edge applications. The proposed architecture integrates a 4 x 4 array of Processing Elements (PEs) for efficient parallel computation and dedicated 4 x 2 Memory Operation Blocks (MOBs) for optimized LOAD/STORE operations, reducing memory bandwidth demands and enhancing data reuse. A switchless mesh torus interconnect network further minimizes power and latency by enabling direct communication between PEs and MOBs, eliminating the need for centralized switching. Through its heterogeneous array design and efficient dataflow, this CGRA architecture addresses the unique computational needs of transformers, offering a scalable pathway to deploy sophisticated machine learning models on edge devices.

Key facts. No citing papers in the map yet (data through 14 Oct 2026). Builds on 2 of its 14 references that are in the map. First posted on arXiv 17 Jul 2025.

Builds on

2 of 14 references.

References · 2

  1. 2020A Survey on Coarse-Grained Reconfigurable Architectures from a Performance Perspectivecited by 4
  2. 2023WaveCert: Translation Validation for Asynchronous Dataflow Programs via Dynamic Fractional Permissionscited by 1

Built on by

Not cited yet.