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Accelerating Transposed Convolutions on FPGA-based Edge Devices

arXiv 2507.07683 ↗First posted 10 Jul 2025cs.AR cs.DC cs.LGcited by 0

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Abstract (arXiv)

Transposed Convolutions (TCONV) enable the up-scaling mechanism within generative Artificial Intelligence (AI) models. However, the predominant Input-Oriented Mapping (IOM) method for implementing TCONV has complex output mapping, overlapping sums, and ineffectual computations. These inefficiencies further exacerbate the performance bottleneck of TCONV and generative models on resource-constrained edge devices. To address this problem, in this paper we propose MM2IM, a hardware-software co-designed accelerator that combines Matrix Multiplication (MatMul) with col2IM to process TCONV layers on resource-constrained edge devices efficiently. Using the SECDA-TFLite design toolkit, we implement MM2IM and evaluate its performance across 261 TCONV problem configurations, achieving an average speedup of 1.9x against a dual-thread ARM Neon optimized CPU baseline. We then evaluate the performance of MM2IM on a range of TCONV layers from well-known generative models achieving up to 4.2x speedup, and compare it against similar resource-constrained TCONV accelerators, outperforming them by at least 2x GOPs/DSP. Finally, we evaluate MM2IM on the DCGAN and pix2pix GAN models, achieving up to 3x speedup and 2.4x energy reduction against the CPU baseline.

Key facts. No citing papers in the map yet (data through 14 Oct 2026). Builds on 10 of its 21 references that are in the map. First posted on arXiv 10 Jul 2025.

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References · 10

  1. 2014Fully Convolutional Networks for Semantic Segmentationcited by 4,859
  2. 2016Image-to-Image Translation with Conditional Adversarial Networkscited by 4,527
  3. 2016Perceptual Losses for Real-Time Style Transfer and Super-Resolutioncited by 2,694
  4. 2015Unsupervised Representation Learning with Deep Convolutional Generative Adversarial Networkscited by 2,054
  5. 2016Accelerating the Super-Resolution Convolutional Neural Networkcited by 394
  6. 2019Generative Modeling for Small-Data Object Detectioncited by 20
  7. 2021SECDA: Efficient Hardware/Software Co-Design of FPGA-based DNN Accelerators for Edge Inferencecited by 12
  8. 2018An Energy-Efficient FPGA-based Deconvolutional Neural Networks Accelerator for Single Image Super-Resolutioncited by 8
  9. 2017A Design Methodology for Efficient Implementation of Deconvolutional Neural Networks on an FPGAcited by 3
  10. 2019Towards Design Methodology of Efficient Fast Algorithms for Accelerating Generative Adversarial Networks on FPGAscited by 3

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