Voltage Mode Winner-Take-All Circuit for Neuromorphic Systems
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Abstract (arXiv)
Recent advances in neuromorphic computing demonstrate on-device learning capabilities with low power consumption. One of the key learning units in these systems is the winner-take-all circuit. In this research, we propose a winner-take-all circuit that can be configured to achieve k-winner and hysteresis properties, simulated in IBM 65 nm node. The circuit dissipated 34.9 μW of power with a latency of 10.4 ns, while processing 1000 inputs. The utility of the circuit is demonstrated for spatial filtering and classification.
Key facts. Cited by 1 paper in the map (data through 14 Oct 2026). Builds on 2 of its 24 references that are in the map. First posted on arXiv 6 Jul 2025.
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2 of 24 references.
References · 2
- 2016Densely Connected Convolutional Networkscited by 6,720
- 2018Neuromorphic Architecture for the Hierarchical Temporal Memorycited by 2
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Citing papers per year: 2025: 1.
1 paper.