UB-Mesh: a Hierarchically Localized nD-FullMesh Datacenter Network Architecture
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Abstract (arXiv)
As the Large-scale Language Models (LLMs) continue to scale, the requisite computational power and bandwidth escalate. To address this, we introduce UB-Mesh, a novel AI datacenter network architecture designed to enhance scalability, performance, cost-efficiency and availability. Unlike traditional datacenters that provide symmetrical node-to-node bandwidth, UB-Mesh employs a hierarchically localized nD-FullMesh network topology. This design fully leverages the data locality of LLM training, prioritizing short-range, direct interconnects to minimize data movement distance and reduce switch usage. Although UB-Mesh's nD-FullMesh topology offers several theoretical advantages, its concrete architecture design, physical implementation and networking system optimization present new challenges. For the actual construction of UB-Mesh, we first design the UB-Mesh-Pod architecture, which is based on a 4D-FullMesh topology. UB-Mesh-Pod is implemented via a suite of hardware components that serve as the foundational building blocks, including specifically-designed NPU, CPU, Low-Radix-Switch (LRS), High-Radix-Switch (HRS), NICs and others. These components are interconnected via a novel Unified Bus (UB) technique, which enables flexible IO bandwidth allocation and hardware resource pooling. For networking system optimization, we propose advanced routing mechanism named All-Path-Routing (APR) to efficiently manage data traffic. These optimizations, combined with topology-aware performance enhancements and robust reliability measures like 64+1 backup design, result in 2.04x higher cost-efficiency, 7.2% higher network availability compared to traditional Clos architecture and 95%+ linearity in various LLM training tasks.
Key facts. Cited by 6 papers in the map (data through 14 Oct 2026). First posted on arXiv 26 Mar 2025.
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Citing papers per year: 2025: 1; 2026: 5.
6 papers.
- 2025Insights into DeepSeek-V3: Scaling Challenges and Reflections on Hardware for AI Architecturescited by 39
- 2026SAC: Disaggregated KV Cache System for Sparse Attention LLMs with CXLcited by 2
- 2026TENT: A Declarative Slice Spraying Engine for Performant and Resilient Data Movement in Disaggregated LLM Servingcited by 1
- 2026Rethinking Network Topologies for Cost-Effective Mixture-of-Experts LLM Servingcited by 0
- 2026ASAP: A Disaggregated and Asynchronous Inference System for MoE Prefillcited by 0
- 2026UBEP: Re-architecting Expert Parallelism Communication Library for Production Superpodscited by 0
- 2026UBEP: Re-architecting Expert Parallelism Communication Library for Production Superpods7 Jul 2026
- 2026ASAP: A Disaggregated and Asynchronous Inference System for MoE Prefill21 Jun 2026
- 2026SAC: Disaggregated KV Cache System for Sparse Attention LLMs with CXL18 Jun 2026
- 2026Rethinking Network Topologies for Cost-Effective Mixture-of-Experts LLM Serving30 Apr 2026
- 2026TENT: A Declarative Slice Spraying Engine for Performant and Resilient Data Movement in Disaggregated LLM Serving1 Apr 2026
- 2025Insights into DeepSeek-V3: Scaling Challenges and Reflections on Hardware for AI Architectures14 May 2025