Understanding Data Movement in Tightly Coupled Heterogeneous Systems: A Case Study with the Grace Hopper Superchip
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Abstract (arXiv)
Heterogeneous supercomputers have become the standard in HPC. GPUs in particular have dominated the accelerator landscape, offering unprecedented performance in parallel workloads and unlocking new possibilities in fields like AI and climate modeling. With many workloads becoming memory-bound, improving the communication latency and bandwidth within the system has become a main driver in the development of new architectures. The Grace Hopper Superchip (GH200) is a significant step in the direction of tightly coupled heterogeneous systems, in which all CPUs and GPUs share a unified address space and support transparent fine grained access to all main memory on the system. We characterize both intra- and inter-node memory operations on the Quad GH200 nodes of the new Swiss National Supercomputing Centre Alps supercomputer, and show the importance of careful memory placement on example workloads, highlighting tradeoffs and opportunities.
Key facts. Cited by 8 papers in the map (data through 7 Oct 2026). First posted on arXiv 21 Aug 2024.
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Citing papers per year: 2025: 5; 2026: 3.
8 papers.
- 2025RadVLM: A Multitask Conversational Vision-Language Model for Radiologycited by 24
- 2025Characterizing and Optimizing LLM Inference Workloads on CPU-GPU Coupled Architecturescited by 8
- 2025SuperOffload: Unleashing the Power of Large-Scale LLM Training on Superchipscited by 6
- 2026SuperInfer: SLO-Aware Rotary Scheduling and Memory Management for LLM Inference on Superchipscited by 2
- 2025GPU-centric Communication Schemes for HPC and ML Applicationscited by 0
- 2025Distributed Equivariant Graph Neural Networks for Large-Scale Electronic Structure Predictioncited by 0
- 2026MALOQ: Massively Accelerated Learning of Operators for Quantum Transportcited by 0
- 2026BOOST: Concurrent Access to Host Memory and HBM to Accelerate LLM Inferencecited by 0
- 2026BOOST: Concurrent Access to Host Memory and HBM to Accelerate LLM Inference11 Sep 2026
- 2026MALOQ: Massively Accelerated Learning of Operators for Quantum Transport27 Jun 2026
- 2026SuperInfer: SLO-Aware Rotary Scheduling and Memory Management for LLM Inference on Superchips28 Jan 2026
- 2025SuperOffload: Unleashing the Power of Large-Scale LLM Training on Superchips25 Sep 2025
- 2025Distributed Equivariant Graph Neural Networks for Large-Scale Electronic Structure Prediction4 Jul 2025
- 2025Characterizing and Optimizing LLM Inference Workloads on CPU-GPU Coupled Architectures16 Apr 2025
- 2025GPU-centric Communication Schemes for HPC and ML Applications31 Mar 2025
- 2025RadVLM: A Multitask Conversational Vision-Language Model for Radiology5 Feb 2025