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Accelerating Depthwise Separable Convolutions on Ultra-Low-Power Devices

arXiv 2406.12478 ↗First posted 18 Jun 2024cs.LG cs.DCcited by 0

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Abstract (arXiv)

Depthwise separable convolutions are a fundamental component in efficient Deep Neural Networks, as they reduce the number of parameters and operations compared to traditional convolutions while maintaining comparable accuracy. However, their low data reuse opportunities make deploying them notoriously difficult. In this work, we perform an extensive exploration of alternatives to fuse the depthwise and pointwise kernels that constitute the separable convolutional block. Our approach aims to minimize time-consuming memory transfers by combining different data layouts. When targeting a commercial ultra-low-power device with a three-level memory hierarchy, the GreenWaves GAP8 SoC, we reduce the latency of end-to-end network execution by up to 11.40%. Furthermore, our kernels reduce activation data movements between L2 and L1 memories by up to 52.97%.

Key facts. No citing papers in the map yet (data through 7 Oct 2026). Builds on 14 of its 18 references that are in the map. First posted on arXiv 18 Jun 2024.

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References · 14

  1. 2017MobileNets: Efficient Convolutional Neural Networks for Mobile Vision Applicationscited by 3,827
  2. 2016Xception: Deep Learning with Depthwise Separable Convolutionscited by 2,320
  3. 2015Deep Compression: Compressing Deep Neural Networks with Pruning, Trained Quantization and Huffman Codingcited by 2,291
  4. 2014cuDNN: Efficient Primitives for Deep Learningcited by 240
  5. 2018CMSIS-NN: Efficient Neural Network Kernels for Arm Cortex-M CPUscited by 116
  6. 2017Hello Edge: Keyword Spotting on Microcontrollerscited by 108
  7. 2020Data Movement Is All You Need: A Case Study on Optimizing Transformerscited by 108
  8. 2021MCUNetV2: Memory-Efficient Patch-based Inference for Tiny Deep Learningcited by 87
  9. 2020DORY: Automatic End-to-End Deployment of Real-World DNNs on Low-Cost IoT MCUscited by 57
  10. 2021DNNFusion: Accelerating Deep Neural Networks Execution with Advanced Operator Fusioncited by 56
  11. 2019PULP-NN: Accelerating Quantized Neural Networks on Parallel Ultra-Low-Power RISC-V Processorscited by 34
  12. 2021Vega: A 10-Core SoC for IoT End-Nodes with DNN Acceleration and Cognitive Wake-Up From MRAM-Based State-Retentive Sleep Modecited by 16
2 more
  1. 2022GVSoC: A Highly Configurable, Fast and Accurate Full-Platform Simulator for RISC-V based IoT Processorscited by 6
  2. 2022Energy-Efficient Adaptive Machine Learning on IoT End-Nodes With Class-Dependent Confidencecited by 3

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