SambaNova SN40L: Scaling the AI Memory Wall with Dataflow and Composition of Experts
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Abstract (arXiv)
Monolithic large language models (LLMs) like GPT-4 have paved the way for modern generative AI applications. Training, serving, and maintaining monolithic LLMs at scale, however, remains prohibitively expensive and challenging. The disproportionate increase in compute-to-memory ratio of modern AI accelerators have created a memory wall, necessitating new methods to deploy AI. Composition of Experts (CoE) is an alternative modular approach that lowers the cost and complexity of training and serving. However, this approach presents two key challenges when using conventional hardware: (1) without fused operations, smaller models have lower operational intensity, which makes high utilization more challenging to achieve; and (2) hosting a large number of models can be either prohibitively expensive or slow when dynamically switching between them. In this paper, we describe how combining CoE, streaming dataflow, and a three-tier memory system scales the AI memory wall. We describe Samba-CoE, a CoE system with 150 experts and a trillion total parameters. We deploy Samba-CoE on the SambaNova SN40L Reconfigurable Dataflow Unit (RDU) - a commercial dataflow accelerator architecture that has been co-designed for enterprise inference and training applications. The chip introduces a new three-tier memory system with on-chip distributed SRAM, on-package HBM, and off-package DDR DRAM. A dedicated inter-RDU network enables scaling up and out over multiple sockets. We demonstrate speedups ranging from 2× to 13× on various benchmarks running on eight RDU sockets compared with an unfused baseline. We show that for CoE inference deployments, the 8-socket RDU Node reduces machine footprint by up to 19×, speeds up model switching time by 15× to 31×, and achieves an overall speedup of 3.7× over a DGX H100 and 6.6× over a DGX A100.
Key facts. Cited by 18 papers in the map (data through 7 Oct 2026). Builds on 34 of its 75 references that are in the map. First posted on arXiv 13 May 2024.
Builds on
34 of 75 references.
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Citing papers per year: 2024: 5; 2025: 9; 2026: 4.
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- 2024Scaling Deep Learning Computation over the Inter-Core Connected Intelligence Processor with T10cited by 5
- 2024Composition of Experts: A Modular Compound AI System Leveraging Large Language Modelscited by 5
- 2025CoServe: Efficient Collaboration-of-Experts (CoE) Model Inference with Limited Memorycited by 5
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- 2025Mixed-Precision Quantization for Language Models: Techniques and Prospectscited by 4
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- 2025Assessing Tenstorrent's RISC-V MatMul Acceleration Capabilitiescited by 1
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- 2026Maia 200: A Software Defined Dataflow System for Large-scale AI Accelerationcited by 0
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- 2026M100: An Orchestrated Dataflow Architecture Powering General AI Computing20 Apr 2026
- 2025Mixed-Precision Quantization for Language Models: Techniques and Prospects19 Oct 2025
- 2025From Loop Nests to Silicon: Mapping AI Workloads onto AMD NPUs with MLIR-AIR16 Oct 2025
- 2025Assessing Tenstorrent's RISC-V MatMul Acceleration Capabilities9 May 2025
- 2025LLM-Assisted Translation of Legacy FORTRAN Codes to C++: A Cross-Platform Study21 Apr 2025
- 2025ObscuraCoder: Powering Efficient Code LM Pre-Training Via Obfuscation Grounding27 Mar 2025
- 2025CoServe: Efficient Collaboration-of-Experts (CoE) Model Inference with Limited Memory4 Mar 2025
- 2024Smoothie: Label Free Language Model Routing6 Dec 2024
- 2024Composition of Experts: A Modular Compound AI System Leveraging Large Language Models2 Dec 2024
- 2024LLM-Inference-Bench: Inference Benchmarking of Large Language Models on AI Accelerators31 Oct 2024
- 2024Scaling Deep Learning Computation over the Inter-Core Connected Intelligence Processor with T109 Aug 2024