An Introduction to the Compute Express Link (CXL) Interconnect
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Abstract (arXiv)
The Compute Express Link (CXL) is an open industry-standard interconnect between processors and devices such as accelerators, memory buffers, smart network interfaces, persistent memory, and solid-state drives. CXL offers coherency and memory semantics with bandwidth that scales with PCIe bandwidth while achieving significantly lower latency than PCIe. All major CPU vendors, device vendors, and datacenter operators have adopted CXL as a common standard. This enables an inter-operable ecosystem that supports key computing use cases including highly efficient accelerators, server memory bandwidth and capacity expansion, multi-server resource pooling and sharing, and efficient peer-to-peer communication. This survey provides an introduction to CXL covering the standards CXL 1.0, CXL 2.0, and CXL 3.0. We further survey CXL implementations, discuss CXL's impact on the datacenter landscape, and future directions.
Key facts. Cited by 9 papers in the map (data through 7 Oct 2026). First posted on arXiv 20 Jun 2023.
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Citing papers per year: 2023: 1; 2024: 1; 2025: 4; 2026: 3.
9 papers.
- 2025PAPI: Exploiting Dynamic Parallelism in Large Language Model Decoding with a Processing-In-Memory-Enabled Computing Systemcited by 19
- 2023ESPN: Memory-Efficient Multi-Vector Information Retrievalcited by 7
- 2025A Cost-Effective Near-Storage Processing Solution for Offline Inference of Long-Context LLMscited by 4
- 2025REIS: A High-Performance and Energy-Efficient Retrieval System with In-Storage Processingcited by 4
- 2024SmartQuant: CXL-based AI Model Store in Support of Runtime Configurable Weight Quantizationcited by 2
- 2026Adaptive KV Cache Reuse for Fast Long-Context LLM Servingcited by 2
- 2026SAC: Disaggregated KV Cache System for Sparse Attention LLMs with CXLcited by 2
- 2025TRACE: Unlocking Effective CXL Bandwidth via Lossless Compression and Precision Scalingcited by 0
- 2026From Tensor Buffer to Distributed Memory Hierarchy: A Survey of KV Cache Management for LLM Servingcited by 0
- 2026From Tensor Buffer to Distributed Memory Hierarchy: A Survey of KV Cache Management for LLM Serving30 Jun 2026
- 2026SAC: Disaggregated KV Cache System for Sparse Attention LLMs with CXL18 Jun 2026
- 2026Adaptive KV Cache Reuse for Fast Long-Context LLM Serving20 May 2026
- 2025TRACE: Unlocking Effective CXL Bandwidth via Lossless Compression and Precision Scaling3 Sep 2025
- 2025REIS: A High-Performance and Energy-Efficient Retrieval System with In-Storage Processing19 Jun 2025
- 2025PAPI: Exploiting Dynamic Parallelism in Large Language Model Decoding with a Processing-In-Memory-Enabled Computing System21 Feb 2025
- 2025A Cost-Effective Near-Storage Processing Solution for Offline Inference of Long-Context LLMs14 Feb 2025
- 2024SmartQuant: CXL-based AI Model Store in Support of Runtime Configurable Weight Quantization17 Jul 2024
- 2023ESPN: Memory-Efficient Multi-Vector Information Retrieval9 Dec 2023