Flex-SFU: Accelerating DNN Activation Functions by Non-Uniform Piecewise Approximation
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Abstract (arXiv)
Modern DNN workloads increasingly rely on activation functions consisting of computationally complex operations. This poses a challenge to current accelerators optimized for convolutions and matrix-matrix multiplications. This work presents Flex-SFU, a lightweight hardware accelerator for activation functions implementing non-uniform piecewise interpolation supporting multiple data formats. Non-Uniform segments and floating-point numbers are enabled by implementing a binary-tree comparison within the address decoding unit. An SGD-based optimization algorithm with heuristics is proposed to find the interpolation function reducing the mean squared error. Thanks to non-uniform interpolation and floating-point support, Flex-SFU achieves on average 22.3x better mean squared error compared to previous piecewise linear interpolation approaches. The evaluation with more than 700 computer vision and natural language processing models shows that Flex-SFU can, on average, improve the end-to-end performance of state-of-the-art AI hardware accelerators by 35.7%, achieving up to 3.3x speedup with negligible impact in the models' accuracy when using 32 segments, and only introducing an area and power overhead of 5.9% and 0.8% relative to the baseline vector processing unit.
Key facts. Cited by 8 papers in the map (data through 14 Oct 2026). First posted on arXiv 8 May 2023.
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Citing papers per year: 2023: 3; 2024: 1; 2025: 2; 2026: 2.
8 papers.
- 2024MARCA: Mamba Accelerator with ReConfigurable Architecturecited by 13
- 2025FP4DiT: Towards Effective Floating Point Quantization for Diffusion Transformerscited by 6
- 2025XAMBA: Enabling Efficient State Space Models on Resource-Constrained Neural Processing Unitscited by 3
- 2023TSSR: A Truncated and Signed Square Root Activation Function for Neural Networkscited by 1
- 2023Stella Nera: A Differentiable Maddness-Based Hardware Accelerator for Efficient Approximate Matrix Multiplicationcited by 1
- 2023RACE-IT: A Reconfigurable Analog Computing Engine for In-Memory Transformer Accelerationcited by 1
- 2026DAPA: Distribution Aware Piecewise Activation Functions for On-Device Transformer Inference and Trainingcited by 0
- 2026APEX: Adaptive Expert Prefetching for Memory-Efficient Edge MoE Inferencecited by 0
- 2026APEX: Adaptive Expert Prefetching for Memory-Efficient Edge MoE Inference12 Aug 2026
- 2026DAPA: Distribution Aware Piecewise Activation Functions for On-Device Transformer Inference and Training19 Mar 2026
- 2025FP4DiT: Towards Effective Floating Point Quantization for Diffusion Transformers19 Mar 2025
- 2025XAMBA: Enabling Efficient State Space Models on Resource-Constrained Neural Processing Units10 Feb 2025
- 2024MARCA: Mamba Accelerator with ReConfigurable Architecture16 Sep 2024
- 2023RACE-IT: A Reconfigurable Analog Computing Engine for In-Memory Transformer Acceleration29 Nov 2023
- 2023Stella Nera: A Differentiable Maddness-Based Hardware Accelerator for Efficient Approximate Matrix Multiplication16 Nov 2023
- 2023TSSR: A Truncated and Signed Square Root Activation Function for Neural Networks9 Aug 2023